MyungJoo Ham wrote:
>
> In S5PV210/S5PC110/Exynos4, ADCMUX channel selection uses ADCMUX
> register, not ADCCON register. This patch corrects the behavior of
> Samsung-ADC for such cpus.
>
> Signed-off-by: MyungJoo Ham <myungjoo.ham@xxxxxxxxxxx>
> Signed-off-by: Kyungmin Park <kyungmin.park@xxxxxxxxxxx>
> --
> v2: No changes from v1. Resubmitted as a series of patches
> ---
> arch/arm/plat-samsung/adc.c | 24
> +++++++++++++++++-------
> arch/arm/plat-samsung/include/plat/regs-adc.h | 1 +
> 2 files changed, 18 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
> index 938f6e9..0233c69 100644
> --- a/arch/arm/plat-samsung/adc.c
> +++ b/arch/arm/plat-samsung/adc.c
> @@ -41,8 +41,10 @@
>
> enum s3c_cpu_type {
> TYPE_S3C24XX,
> - TYPE_S3C64XX
> + TYPE_S3C64XX,
> + TYPE_S5P,
> };
How about S5PC100? Following is better for next if we cannot distinguish it
by CPU.
-enum s3c_cpu_type {
- TYPE_S3C24XX,
- TYPE_S3C64XX
+enum samsung_adc_type {
+ TYPE_ADC24, /* S3C24XX */
+ TYPE_ADC64, /* S3C64XX, S5P64X0, S5PC100 */
+ TYPE_ADCV3 /* S5PV210, EXYNOS4210 */
};
...
TYPE_ADCV1 and V2?...
Of course, the name can be changed...
> +#define S3C64XX_OR_LATER(type) ((type) == TYPE_S3C64XX || (type) ==
> TYPE_S5P)
>
> struct s3c_adc_client {
> struct platform_device *pdev;
> @@ -93,6 +95,7 @@ static inline void s3c_adc_select(struct adc_device
*adc,
> struct s3c_adc_client *client)
> {
> unsigned con = readl(adc->regs + S3C2410_ADCCON);
> + enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)-
> >driver_data;
>
> client->select_cb(client, 1);
>
> @@ -100,8 +103,12 @@ static inline void s3c_adc_select(struct adc_device
*adc,
> con &= ~S3C2410_ADCCON_STDBM;
> con &= ~S3C2410_ADCCON_STARTMASK;
>
> - if (!client->is_ts)
> - con |= S3C2410_ADCCON_SELMUX(client->channel);
> + if (!client->is_ts) {
> + if (cpu == TYPE_S5P)
> + writel(client->channel & 0xf, adc->regs +
> S5P_ADCMUX);
> + else
> + con |= S3C2410_ADCCON_SELMUX(client->channel);
> + }
>
> writel(con, adc->regs + S3C2410_ADCCON);
> }
> @@ -287,8 +294,8 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
>
> client->nr_samples--;
>
> - if (cpu == TYPE_S3C64XX) {
> - /* S3C64XX ADC resolution is 12-bit */
> + if (S3C64XX_OR_LATER(cpu)) {
> + /* S3C64XX/S5P ADC resolution is 12-bit */
> data0 &= 0xfff;
> data1 &= 0xfff;
> } else {
> @@ -314,7 +321,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
> }
>
> exit:
> - if (cpu == TYPE_S3C64XX) {
Or (if we use s3c_cpu_type)
+ if (cpu != TYPE_S3C24XX) {
> + if (S3C64XX_OR_LATER(cpu)) {
> /* Clear ADC interrupt */
> writel(0, adc->regs + S3C64XX_ADCCLRINT);
> }
> @@ -388,7 +395,7 @@ static int s3c_adc_probe(struct platform_device *pdev)
> clk_enable(adc->clk);
>
> tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
> - if (platform_get_device_id(pdev)->driver_data == TYPE_S3C64XX) {
> + if (S3C64XX_OR_LATER(platform_get_device_id(pdev)->driver_data)) {
> /* Enable 12-bit ADC resolution */
> tmp |= S3C64XX_ADCCON_RESSEL;
> }
> @@ -478,6 +485,9 @@ static struct platform_device_id s3c_adc_driver_ids[]
= {
> }, {
> .name = "s3c64xx-adc",
> .driver_data = TYPE_S3C64XX,
> + }, {
> + .name = "s5p-adc",
> + .driver_data = TYPE_S5P,
> },
> { }
> };
> diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h
b/arch/arm/plat-
> samsung/include/plat/regs-adc.h
> index 7554c4f..035e8c3 100644
> --- a/arch/arm/plat-samsung/include/plat/regs-adc.h
> +++ b/arch/arm/plat-samsung/include/plat/regs-adc.h
> @@ -21,6 +21,7 @@
> #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
> #define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14)
> #define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18)
> +#define S5P_ADCMUX S3C2410_ADCREG(0x1C)
> #define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)
>
>
> --
> 1.7.4.1
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@xxxxxxxxxxx>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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