Add clkdev support for Samsung's Exynos4 platform.
Signed-off-by: Thomas Abraham <thomas.ab@xxxxxxxxxxx>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-exynos4/clock.c | 63 +++++++++++++++++++++++++--
arch/arm/mach-exynos4/include/mach/clkdev.h | 7 +++
arch/arm/mach-exynos4/time.c | 2 +
4 files changed, 69 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/mach-exynos4/include/mach/clkdev.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8d010f2..452e1c1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -786,6 +786,7 @@ config ARCH_EXYNOS4
select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO
select HAVE_CLK
+ select CLKDEV_LOOKUP
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
select HAVE_S3C_RTC if RTC_CLASS
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 871f9d5..901fa51 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -404,41 +404,49 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1<<24),
}, {
.name = "csis",
+ .devname = "s5p-mipi-csis.0",
.id = 0,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "csis",
+ .devname = "s5p-mipi-csis.1",
.id = 1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "fimc",
+ .devname = "exynos4-fimc.0",
.id = 0,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "fimc",
+ .devname = "exynos4-fimc.1",
.id = 1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "fimc",
+ .devname = "exynos4-fimc.2",
.id = 2,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "fimc",
+ .devname = "exynos4-fimc.3",
.id = 3,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "fimd",
+ .devname = "s5pv310-fb.0",
.id = 0,
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "fimd",
+ .devname = "s5pv310-fb.1",
.id = 1,
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 0),
@@ -450,31 +458,35 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 3),
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.0",
.id = 0,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.1",
.id = 1,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.2",
.id = 2,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "hsmmc",
+ .devname = "s3c-sdhci.3",
.id = 3,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 8),
}, {
- .name = "hsmmc",
- .id = 4,
+ .name = "dwmmc",
+ .id = -1,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9),
@@ -486,11 +498,13 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 10),
}, {
.name = "pdma",
+ .devname = "s3c-pl330.0",
.id = 0,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "pdma",
+ .devname = "s3c-pl330.1",
.id = 1,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 1),
@@ -527,31 +541,37 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 13),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
+ .devname = "s3c64xx-spi.2",
.id = 2,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "iis",
+ .devname = "samsung-i2s.0",
.id = 0,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "iis",
+ .devname = "samsung-i2s.1",
.id = 1,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "iis",
+ .devname = "samsung-i2s.2",
.id = 2,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 21),
@@ -567,48 +587,56 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 0),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.0",
.id = 0,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.1",
.id = 1,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.2",
.id = 2,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.3",
.id = 3,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.4",
.id = 4,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.5",
.id = 5,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.6",
.id = 6,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
+ .devname = "s3c2440-i2c.7",
.id = 7,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
@@ -689,31 +717,37 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "uart",
+ .devname = "s5pv210-uart.0",
.id = 0,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "uart",
+ .devname = "s5pv210-uart.1",
.id = 1,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
+ .devname = "s5pv210-uart.2",
.id = 2,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
+ .devname = "s5pv210-uart.3",
.id = 3,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
+ .devname = "s5pv210-uart.4",
.id = 4,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "uart",
+ .devname = "s5pv210-uart.5",
.id = 5,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 5),
@@ -839,6 +873,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "uclk1",
+ .devname = "s5pv210-uart.0",
.id = 0,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 0),
@@ -849,6 +884,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
+ .devname = "s5pv210-uart.1",
.id = 1,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 4),
@@ -859,6 +895,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
+ .devname = "s5pv210-uart.2",
.id = 2,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 8),
@@ -869,6 +906,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
+ .devname = "s5pv210-uart.3",
.id = 3,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 12),
@@ -889,6 +927,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_csis",
+ .devname = "s5p-mipi-csis.0",
.id = 0,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 24),
@@ -899,6 +938,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_csis",
+ .devname = "s5p-mipi-csis.1",
.id = 1,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 28),
@@ -909,6 +949,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
+ .devname = "exynos4-fimc.0",
.id = 0,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 16),
@@ -919,6 +960,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
+ .devname = "exynos4-fimc.1",
.id = 1,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 20),
@@ -929,6 +971,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
+ .devname = "exynos4-fimc.0",
.id = 0,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 0),
@@ -939,6 +982,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
+ .devname = "exynos4-fimc.1",
.id = 1,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 4),
@@ -949,6 +993,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
+ .devname = "exynos4-fimc.2",
.id = 2,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 8),
@@ -959,6 +1004,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
+ .devname = "exynos4-fimc.3",
.id = 3,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 12),
@@ -969,6 +1015,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimd",
+ .devname = "s5pv310-fb.0",
.id = 0,
.enable = exynos4_clksrc_mask_lcd0_ctrl,
.ctrlbit = (1 << 0),
@@ -979,6 +1026,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimd",
+ .devname = "s5pv310-fb.1",
.id = 1,
.enable = exynos4_clksrc_mask_lcd1_ctrl,
.ctrlbit = (1 << 0),
@@ -999,6 +1047,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
+ .devname = "s3c64xx-spi.0",
.id = 0,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16),
@@ -1009,6 +1058,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
+ .devname = "s3c64xx-spi.1",
.id = 1,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20),
@@ -1019,6 +1069,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
+ .devname = "s3c64xx-spi.2",
.id = 2,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24),
@@ -1037,6 +1088,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "s3c-sdhci.0",
.id = 0,
.parent = &clk_dout_mmc0.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
@@ -1046,6 +1098,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "s3c-sdhci.1",
.id = 1,
.parent = &clk_dout_mmc1.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
@@ -1055,6 +1108,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "s3c-sdhci.2",
.id = 2,
.parent = &clk_dout_mmc2.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
@@ -1064,6 +1118,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
+ .devname = "s3c-sdhci.3",
.id = 3,
.parent = &clk_dout_mmc3.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
@@ -1072,8 +1127,8 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
}, {
.clk = {
- .name = "sclk_mmc",
- .id = 4,
+ .name = "sclk_dwmmc",
+ .id = -1,
.parent = &clk_dout_mmc4.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 16),
diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h
new file mode 100644
index 0000000..1247f5e
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_EXYNOS4_CLKDEV_H__
+#define __MACH_EXYNOS4_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-exynos4/time.c b/arch/arm/mach-exynos4/time.c
index 86b9fa0..cb63f97 100644
--- a/arch/arm/mach-exynos4/time.c
+++ b/arch/arm/mach-exynos4/time.c
@@ -262,6 +262,7 @@ static void __init exynos4_timer_resources(void)
clk_enable(timerclk);
tmpdev.id = 2;
+ tmpdev.dev.init_name = "s3c24xx-pwm.2";
tin2 = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin2))
panic("failed to get pwm-tin2 clock for system timer");
@@ -272,6 +273,7 @@ static void __init exynos4_timer_resources(void)
clk_enable(tin2);
tmpdev.id = 4;
+ tmpdev.dev.init_name = "s3c24xx-pwm.4";
tin4 = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin4))
panic("failed to get pwm-tin4 clock for system timer");
--
1.6.6.rc2
--
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