On Fri, Oct 8, 2010 at 7:29 PM, Kukjin Kim <kgene.kim@xxxxxxxxxxx> wrote:
> Seungwhan Youn wrote:
>>
>> This patch adds EPLL specific clock get_rate/set_rate operations
>> on S5PV210.
>>
>> Signed-off-by: Seungwhan Youn <sw.youn@xxxxxxxxxxx>
>> ---
>> Âarch/arm/mach-s5pv210/clock.c    Â|  95
>> ++++++++++++++++++++++++++++++++++
>> Âarch/arm/plat-s5p/include/plat/pll.h | Â Â2 +
>> Â2 files changed, 97 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
>> index bcbe7e9..affa5a0 100644
>> --- a/arch/arm/mach-s5pv210/clock.c
>> +++ b/arch/arm/mach-s5pv210/clock.c
>> @@ -1003,6 +1003,97 @@ static struct clksrc_clk *sysclks[] = {
>> Â Â Â &clk_sclk_spdif,
>> Â};
>>
>> +static int s5pv210_epll_enable(struct clk *clk, int enable)
>> +{
>> + Â Â unsigned int ctrlbit = clk->ctrlbit;
>> + Â Â unsigned int epll_con = __raw_readl(S5P_EPLL_CON0) & ~ctrlbit;
>> +
>> + Â Â if (enable)
>> + Â Â Â Â Â Â __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON0);
>> + Â Â else
>> + Â Â Â Â Â Â __raw_writel(epll_con, S5P_EPLL_CON0);
>> +
>> + Â Â return 0;
>> +}
>> +
>
> Maybe if we move s5p64x0_epll_enable() to common part i.e.,
> plat-s5p/clock.c, we can use common_epll_enable() in here.
> Of course, need to sort out the regarding definitions such as
> S5PXX_EPLL_CON0...
>
Okay, I'll fix.
>> +static unsigned long s5pv210_epll_get_rate(struct clk *clk)
>> +{
>> + Â Â return clk->rate;
>> +}
>> +
>> +static u32 epll_div[][6] = {
>> + Â Â { Â48000000, 0, 48, 3, 3, 0 },
>> + Â Â { Â96000000, 0, 48, 3, 2, 0 },
>> + Â Â { 144000000, 1, 72, 3, 2, 0 },
>> + Â Â { 192000000, 0, 48, 3, 1, 0 },
>> + Â Â { 288000000, 1, 72, 3, 1, 0 },
>> + Â Â { Â32750000, 1, 65, 3, 4, 35127 },
>> + Â Â { Â32768000, 1, 65, 3, 4, 35127 },
>> + Â Â { Â45158400, 0, 45, 3, 3, 10355 },
>> + Â Â { Â45000000, 0, 45, 3, 3, 10355 },
>> + Â Â { Â45158000, 0, 45, 3, 3, 10355 },
>> + Â Â { Â49125000, 0, 49, 3, 3, 9961 },
>> + Â Â { Â49152000, 0, 49, 3, 3, 9961 },
>> + Â Â { Â67737600, 1, 67, 3, 3, 48366 },
>> + Â Â { Â67738000, 1, 67, 3, 3, 48366 },
>> + Â Â { Â73800000, 1, 73, 3, 3, 47710 },
>> + Â Â { Â73728000, 1, 73, 3, 3, 47710 },
>> + Â Â { Â36000000, 1, 32, 3, 4, 0 },
>> + Â Â { Â60000000, 1, 60, 3, 3, 0 },
>> + Â Â { Â72000000, 1, 72, 3, 3, 0 },
>> + Â Â { Â80000000, 1, 80, 3, 3, 0 },
>> + Â Â { Â84000000, 0, 42, 3, 2, 0 },
>> + Â Â { Â50000000, 0, 50, 3, 3, 0 },
>> +};
>> +
>> +static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
>> +{
>> + Â Â unsigned int epll_con, epll_con_k;
>> + Â Â unsigned int i;
>> +
>> + Â Â /* Return if nothing changed */
>> + Â Â if (clk->rate == rate)
>> + Â Â Â Â Â Â return 0;
>> +
>> + Â Â epll_con = __raw_readl(S5P_EPLL_CON0);
>> + Â Â epll_con_k = __raw_readl(S5P_EPLL_CON1);
>> +
>> + Â Â epll_con_k &= ~(PLL90XX_KDIV_MASK << PLL90XX_KDIV_SHIFT);
>> + Â Â epll_con &= ~(PLL90XX_VSEL_MASK << PLL90XX_VSEL_SHIFT |
>> + Â Â Â Â Â Â Â Â Â Â PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT |
>> + Â Â Â Â Â Â Â Â Â Â PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT |
>> + Â Â Â Â Â Â Â Â Â Â PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT);
>> +
>> + Â Â for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
>> + Â Â Â Â Â Â if (epll_div[i][0] == rate) {
>> + Â Â Â Â Â Â Â Â Â Â epll_con_k |= epll_div[i][5] << 0;
>> + Â Â Â Â Â Â Â Â Â Â epll_con |= (epll_div[i][1] << PLL90XX_VSEL_SHIFT |
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â epll_div[i][2] <<
>> PLL90XX_MDIV_SHIFT |
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â epll_div[i][3] <<
>> PLL90XX_PDIV_SHIFT |
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â epll_div[i][4] <<
>> PLL90XX_SDIV_SHIFT);
>> + Â Â Â Â Â Â Â Â Â Â break;
>> + Â Â Â Â Â Â }
>> + Â Â }
>> +
>> + Â Â if (i == ARRAY_SIZE(epll_div)) {
>> + Â Â Â Â Â Â printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â __func__);
>> + Â Â Â Â Â Â return -EINVAL;
>> + Â Â }
>> +
>> + Â Â __raw_writel(epll_con, S5P_EPLL_CON0);
>> + Â Â __raw_writel(epll_con_k, S5P_EPLL_CON1);
>> +
>> + Â Â clk->rate = rate;
>> +
>> + Â Â return 0;
>> +}
>> +
>
> Same...
This also, I'll fix it.
(snip)
Thanks,
Claude
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