From: Seungwhan Youn <sw.youn@xxxxxxxxxxx>
This patch fixes EPLL_CON MASK settings which did not contain its
shift values when set epll rate on S5PC100.
Signed-off-by: Seungwhan Youn <sw.youn@xxxxxxxxxxx>
Signed-off-by: Kukjin Kim <kgene.kim@xxxxxxxxxxx>
---
arch/arm/mach-s5pc100/clock.c | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 084abd1..ff125b4 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -323,7 +323,9 @@ static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
epll_con = __raw_readl(S5P_EPLL_CON);
- epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
+ epll_con &= ~((PLL65XX_MDIV_MASK << PLL65XX_MDIV_SHIFT) |
+ (PLL65XX_PDIV_MASK << PLL65XX_PDIV_SHIFT) |
+ (PLL65XX_SDIV_MASK << PLL65XX_SDIV_SHIFT));
for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
if (epll_div[i][0] == rate) {
--
1.6.2.5
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