On Wed, Jul 07, 2010 at 08:27:53AM +0900, Kukjin Kim wrote: > Russell King wrote: > > What is the spacing of chunks of memory, and minimum alignment of those > > chunks in physical address space? > > Some S5PC110(MCP D-type) has only available 80MiB in a bank. > So the space accounts for 432MiB in a DMC0, but larger memory(256MiB + > 128MiB) exists in a DMC1. Ok. > As you know, the size of a section should be a power of 2 and a physical > address space of a section should be contiguous. > If a section size is greater than 16MiB, a section have a hole. So the > SECTION_SIZE_BITS should be 16MiB. Where is this hole? Please show it as a diagram similar to the one you've produced below. > > Also, what is the maximum physical address which memory can be located? > > Following is memory map of S5PV210/S5PC110. > > 0x80000000 ------------------- > | | > 0x70000000 | | > | | > 0x60000000 | DMC 1 | up to 1GiB > | | > 0x50000000 | | > | | > 0x40000000 ----------------- > | | > 0x30000000 | DMC 0 | up to 512MiB > | | > 0x20000000 ------------------- Right, so MAX_PHYSMEM_BITS is 31 and not 32 as you don't have memory at or above 0x80000000. This will immediately halve the amount of sparsemem supporting structures irrespective of the SECTION_SIZE_BITS value. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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