On Thu, Oct 15, 2009 at 02:48:18PM +0900, Thomas Abraham wrote:
> The third base clock option for SDHCI controller in S3C64XX is
> mout_epll. This patch removes mmc_bus clock and uses mout_epll
> as the third clock option for SDHCI base clock.
I thought the MMC bus clock was the one that was gated through the
SCLK_MMC0 and the CLKSRC_MMC0 divider system which takes not only the
mout_epll, but dout_epll, fin_epll and the 27m clock, as so:
static struct clk *clkset_spi_mmc_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
&clk_fin_epll,
&clk_27m,
};
So I don't think this change is the right one but I don't have any
docummentation to hand as I'm currently attending ELC09.
> Signed-off-by: Thomas Abraham <thomas.ab@xxxxxxxxxxx>
> ---
> arch/arm/mach-s3c6410/setup-sdhci.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-s3c6410/setup-sdh2Aci.c b/arch/arm/mach-s3c6410/setup-sdhci.c
> index 20666f3..aaac505 100644
> --- a/arch/arm/mach-s3c6410/setup-sdhci.c
> +++ b/arch/arm/mach-s3c6410/setup-sdhci.c
> @@ -29,7 +29,7 @@
> char *s3c6410_hsmmc_clksrcs[4] = {
> [0] = "hsmmc",
> [1] = "hsmmc",
> - [2] = "mmc_bus",
> + [2] = "mout_epll",
> /* [3] = "48m", - note not succesfully used yet */
> };
>
> --
> 1.5.3.4
>
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