On Fri, 2025-01-24 at 15:17 -0500, Matthew Rosato wrote:
> For each zdev, record whether or not CLP indicates relaxed translation
> capability for the associated device group.
>
> Signed-off-by: Matthew Rosato <mjrosato@xxxxxxxxxxxxx>
> ---
> arch/s390/include/asm/pci.h | 2 +-
> arch/s390/include/asm/pci_clp.h | 4 +++-
> arch/s390/pci/pci_clp.c | 1 +
> 3 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h
> index 474e1f8d1d3c..8fe4c7a72c0b 100644
> --- a/arch/s390/include/asm/pci.h
> +++ b/arch/s390/include/asm/pci.h
> @@ -144,7 +144,7 @@ struct zpci_dev {
> u8 util_str_avail : 1;
> u8 irqs_registered : 1;
> u8 tid_avail : 1;
> - u8 reserved : 1;
> + u8 rtr_avail : 1; /* Relaxed translation allowed */
> unsigned int devfn; /* DEVFN part of the RID*/
>
> u8 pfip[CLP_PFIP_NR_SEGMENTS]; /* pci function internal path */
> diff --git a/arch/s390/include/asm/pci_clp.h b/arch/s390/include/asm/pci_clp.h
> index 3fff2f7095c8..7ebff39c84b3 100644
> --- a/arch/s390/include/asm/pci_clp.h
> +++ b/arch/s390/include/asm/pci_clp.h
> @@ -156,7 +156,9 @@ struct clp_rsp_query_pci_grp {
> u16 : 4;
> u16 noi : 12; /* number of interrupts */
> u8 version;
> - u8 : 6;
> + u8 : 2;
> + u8 rtr : 1; /* Relaxed translation requirement */
> + u8 : 3;
> u8 frame : 1;
> u8 refresh : 1; /* TLB refresh mode */
> u16 : 3;
> diff --git a/arch/s390/pci/pci_clp.c b/arch/s390/pci/pci_clp.c
> index 14bf7e8d06b7..27248686e588 100644
> --- a/arch/s390/pci/pci_clp.c
> +++ b/arch/s390/pci/pci_clp.c
> @@ -112,6 +112,7 @@ static void clp_store_query_pci_fngrp(struct zpci_dev *zdev,
> zdev->version = response->version;
> zdev->maxstbl = response->maxstbl;
> zdev->dtsm = response->dtsm;
> + zdev->rtr_avail = response->rtr;
>
> switch (response->version) {
> case 1:
Checked the bit positions and as discussed out of band I gave the whole
series a try too. So feel free to add:
Reviewed-by: Niklas Schnelle <schnelle@xxxxxxxxxxxxx>
Tested-by: Niklas Schnelle <schnelle@xxxxxxxxxxxxx>
