Use the "Q" instead of "R" constraint to correctly reflect the instruction format of the tm instruction: the first operand is a memory reference without index register and short displacement. The "R" constraint indicates a memory reference with index register instead. This may lead to compile errors like: arch/s390/include/asm/bitops.h: Assembler messages: arch/s390/include/asm/bitops.h:60: Error: operand 1: syntax error; missing ')' after base register arch/s390/include/asm/bitops.h:60: Error: operand 2: syntax error; ')' not allowed here arch/s390/include/asm/bitops.h:60: Error: junk at end of line: `,4' Reported-by: Nathan Chancellor <nathan@xxxxxxxxxx> Closes: https://lore.kernel.org/r/20250122-s390-fix-std-for-gcc-15-v1-1-8b00cadee083@xxxxxxxxxx Fixes: b2bc1b1a77c0 ("s390/bitops: Provide optimized arch_test_bit()") Signed-off-by: Heiko Carstens <hca@xxxxxxxxxxxxx> --- arch/s390/include/asm/bitops.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/s390/include/asm/bitops.h b/arch/s390/include/asm/bitops.h index 15aa64e3020e..d5125296ade2 100644 --- a/arch/s390/include/asm/bitops.h +++ b/arch/s390/include/asm/bitops.h @@ -60,7 +60,7 @@ static __always_inline bool arch_test_bit(unsigned long nr, const volatile unsig asm volatile( " tm %[addr],%[mask]\n" : "=@cc" (cc) - : [addr] "R" (*addr), [mask] "I" (mask) + : [addr] "Q" (*addr), [mask] "I" (mask) ); return cc == 3; } -- 2.45.2
