On Mon, Apr 22, 2024 at 05:35:08PM +0200, Gerd Bayer wrote:
> From: Ben Segal <bpsegal@xxxxxxxxxx>
>
> Many PCI adapters can benefit or even require full 64bit read
> and write access to their registers. In order to enable work on
> user-space drivers for these devices add two new variations
> vfio_pci_core_io{read|write}64 of the existing access methods
> when the architecture supports 64-bit ioreads and iowrites.
>
> Since these access methods are instantiated on 64bit architectures,
> only, their use in vfio_pci_core_do_io_rw() is restricted by conditional
> compiles to these architectures.
>
> Signed-off-by: Ben Segal <bpsegal@xxxxxxxxxx>
> Co-developed-by: Gerd Bayer <gbayer@xxxxxxxxxxxxx>
> Signed-off-by: Gerd Bayer <gbayer@xxxxxxxxxxxxx>
> ---
> Hi all,
>
> we've successfully used this patch with a user-mode driver for a PCI
> device that requires 64bit register read/writes on s390. A quick grep
> showed that there are several other drivers for PCI devices in the kernel
> that use readq/writeq and eventually could use this, too.
> So we decided to propose this for general inclusion.
>
> Thank you,
> Gerd Bayer
>
> Changes v1 -> v2:
> - On non 64bit architecture use at most 32bit accesses in
> vfio_pci_core_do_io_rw and describe that in the commit message.
> - Drop the run-time error on 32bit architectures.
> - The #endif splitting the "else if" is not really fortunate, but I'm
> open to suggestions.
Provide a iowrite64() that does back to back writes for 32 bit?
Jason
