On Tue, 2023-05-16 at 23:36 -0700, Christoph Hellwig wrote:
> On Mon, May 15, 2023 at 05:08:41PM +0800, Baoquan He wrote:
> > +#define ioremap_wc(addr, size) \
> > + ioremap_prot((addr), (size), pgprot_val(pgprot_writecombine(PAGE_KERNEL)))
>
> I'd move this out of line and just apply mio_wb_bit_mask directly
> instead of the unbox/box/unbox/box dance.
>
> > +#define ioremap_wt(addr, size) \
> > + ioremap_prot((addr), (size), pgprot_val(pgprot_writethrough(PAGE_KERNEL)))
>
> and just define this to ioremap_wc. Note that defining _wt to _wc is
> very odd and seems wrong, but comes from the existing code. Maybe the
> s390 maintainers can chime on on the background and we can add a comment
> while we're at it.
I'm a bit confused where you see ioremap_wt() defined to ioremap_wc()
in the existing code? Our current definitions are:
void __iomem *ioremap_wc(phys_addr_t addr, size_t size)
{
return __ioremap(addr, size,
pgprot_writecombine(PAGE_KERNEL));
}
void __iomem *ioremap_wt(phys_addr_t addr, size_t size)
{
return __ioremap(addr, size,
pgprot_writethrough(PAGE_KERNEL));
}
Now if we don't have support for the enhanced PCI load/store
instructions (memory I/O aka MIO) then yes this gets ignored and both
.._wc() and .._wt() act the same but if we do have them
pgprot_writecombine() / pgprot_writethrough() set respectively clear
the mio_wb bit in the PTE. It's a bit odd here because the exact
position of the bit is read from a firmware interface and could in
theory change but other than that it looks fine to me and yes I agree
that it would be odd and broken to define _wt to _wc.
Thanks,
Niklas
