Instructions on s390 must be halfword aligned.
Add two tests for that.
v4 -> v5:
* fix miscompile due to missing barrier (thanks Thomas & Janosch)
* fix issues with clang (thanks Thomas)
v3 -> v4:
* zero whole register with xgr (thanks Janosch)
* pick up tags (thanks Janosch)
v2 -> v3:
* pick up R-b (thanks Janosch)
* use br instead of bcr (thanks Claudio)
* use text section instead of rodata for ex target (thanks Claudio)
* fix label position (thanks Claudio)
v1 -> v2:
* rebase
* use PSW macros
* simplify odd psw test (thanks Claudio)
* rename some identifiers
* pick up R-b (thanks Claudio)
Nina Schoetterl-Glausch (3):
s390x/spec_ex: Use PSW macro
s390x/spec_ex: Add test introducing odd address into PSW
s390x/spec_ex: Add test of EXECUTE with odd target address
s390x/spec_ex.c | 85 +++++++++++++++++++++++++++++++++++++++++++------
1 file changed, 76 insertions(+), 9 deletions(-)
Range-diff against v4:
1: c00f8aa2 = 1: cdfa2083 s390x/spec_ex: Use PSW macro
2: d9e3f6e0 ! 2: 5bf32702 s390x/spec_ex: Add test introducing odd address into PSW
@@ s390x/spec_ex.c: static int psw_bit_12_is_1(void)
return check_invalid_psw();
}
-+extern char misaligned_code[];
++extern char misaligned_code_pre[];
+asm ( ".balign 2\n"
++"misaligned_code_pre:\n"
+" . = . + 1\n"
-+"misaligned_code:\n"
+" larl %r0,0\n"
+" br %r1\n"
+);
+
+static int psw_odd_address(void)
+{
-+ struct psw odd = PSW_WITH_CUR_MASK((uint64_t)&misaligned_code);
++ struct psw odd = PSW_WITH_CUR_MASK(((uint64_t)&misaligned_code_pre) + 1);
+ uint64_t executed_addr;
+
+ expect_invalid_psw(odd);
@@ s390x/spec_ex.c: static int psw_bit_12_is_1(void)
+ : [fixup_addr] "=&T" (fixup_psw.addr),
+ [executed_addr] "=d" (executed_addr)
+ : [odd_psw] "Q" (odd)
-+ : "cc", "%r0", "%r1"
++ : "cc", "%r0", "%r1", "memory" /* Compiler barrier like in load_psw */
+ );
+
+ if (!executed_addr) {
3: 7ea75611 ! 3: 14af5979 s390x/spec_ex: Add test of EXECUTE with odd target address
@@ s390x/spec_ex.c: static int short_psw_bit_12_is_0(void)
+
+ asm volatile ( ".pushsection .text.ex_odd\n"
+ " .balign 2\n"
-+ "pre_odd_ex_target:\n"
++ "pre_odd_ex_target%=:\n"
+ " . = . + 1\n"
+ " lr %[to],%[from]\n"
+ " .popsection\n"
+
-+ " larl %[pre_target_addr],pre_odd_ex_target\n"
++ " larl %[pre_target_addr],pre_odd_ex_target%=\n"
+ " ex 0,1(%[pre_target_addr])\n"
+ : [pre_target_addr] "=&a" (pre_target_addr),
+ [to] "+d" (to)
base-commit: 5b5d27da2973b20ec29b18df4d749fb2190458af
--
2.37.2
