Instructions on s390 must be halfword aligned.
Add two tests for that.
These currently fail when using TCG, Ilya Leoshkevich <iii@xxxxxxxxxxxxx>
posted fixes to the qemu mailing list.
v3 -> v4:
* zero whole register with xgr (thanks Janosch)
* pick up tags (thanks Janosch)
v2 -> v3:
* pick up R-b (thanks Janosch)
* use br instead of bcr (thanks Claudio)
* use text section instead of rodata for ex target (thanks Claudio)
* fix label position (thanks Claudio)
v1 -> v2:
* rebase
* use PSW macros
* simplify odd psw test (thanks Claudio)
* rename some identifiers
* pick up R-b (thanks Claudio)
Nina Schoetterl-Glausch (3):
s390x/spec_ex: Use PSW macro
s390x/spec_ex: Add test introducing odd address into PSW
s390x/spec_ex: Add test of EXECUTE with odd target address
s390x/spec_ex.c | 85 +++++++++++++++++++++++++++++++++++++++++++------
1 file changed, 76 insertions(+), 9 deletions(-)
Range-diff against v3:
1: 6ae1eb7d = 1: c00f8aa2 s390x/spec_ex: Use PSW macro
2: a0d02438 ! 2: d9e3f6e0 s390x/spec_ex: Add test introducing odd address into PSW
@@ Commit message
the odd address.
Add a test for this.
+ Acked-by: Janosch Frank <frankja@xxxxxxxxxxxxx>
Signed-off-by: Nina Schoetterl-Glausch <nsg@xxxxxxxxxxxxx>
## s390x/spec_ex.c ##
@@ s390x/spec_ex.c: static int psw_bit_12_is_1(void)
+
+ expect_invalid_psw(odd);
+ fixup_psw.mask = extract_psw_mask();
-+ asm volatile ( "xr %%r0,%%r0\n"
++ asm volatile ( "xgr %%r0,%%r0\n"
+ " larl %%r1,0f\n"
+ " stg %%r1,%[fixup_addr]\n"
+ " lpswe %[odd_psw]\n"
3: e771deeb ! 3: 7ea75611 s390x/spec_ex: Add test of EXECUTE with odd target address
@@ Commit message
specification exception occurs.
Add a test for this.
+ Reviewed-by: Janosch Frank <frankja@xxxxxxxxxxxxx>
Signed-off-by: Nina Schoetterl-Glausch <nsg@xxxxxxxxxxxxx>
## s390x/spec_ex.c ##
base-commit: 20de8c3b54078ebc3df0b47344f9ce55bf52b7a5
--
2.39.1
