Test that specification exceptions cause the correct interruption code
during both normal and transactional execution.
TCG fails the tests setting an invalid PSW bit.
I had a look at how best to fix it, but where best to check for early
PSW exceptions was not immediately clear to me. Ideas welcome.
v6 -> v7
assert that we're expecting the invalid PSW we're seeing
rebased onto master
picked up tags (thanks Nico & Janosch)
comments and style changes
v5 -> v6
rebased onto master
comments and style changes
v4 -> v5
add lpsw with invalid bit 12 test
TCG fails as with lpswe but must also invert bit 12
update copyright statement
add comments
cleanups and style fixes
v3 -> v4
remove iterations argument in order to simplify the code
for manual performance testing adding a for loop is easy
move report out of fixup_invalid_psw
simplify/improve readability of triggers
use positive error values
v2 -> v3
remove non-ascii symbol
clean up load_psw
fix nits
v1 -> v2
Add license and test description
Split test patch into normal test and transactional execution test
Add comments to
invalid PSW fixup function
with_transaction
Rename some variables/functions
Pass mask as single parameter to asm
Get rid of report_info_if macro
Introduce report_pass/fail and use them
Janis Schoetterl-Glausch (2):
s390x: Add specification exception test
s390x: Test specification exceptions during transaction
s390x/Makefile | 1 +
lib/s390x/asm/arch_def.h | 6 +
s390x/spec_ex.c | 392 +++++++++++++++++++++++++++++++++++++++
s390x/unittests.cfg | 3 +
4 files changed, 402 insertions(+)
create mode 100644 s390x/spec_ex.c
Range-diff against v6:
1: bbfb5d40 ! 1: a239437a s390x: Add specification exception test
@@ Commit message
Generate specification exceptions and check that they occur.
Signed-off-by: Janis Schoetterl-Glausch <scgl@xxxxxxxxxxxxx>
+ Reviewed-by: Nico Boehr <nrb@xxxxxxxxxxxxx>
+ Reviewed-by: Janosch Frank <frankja@xxxxxxxxxxxxx>
## s390x/Makefile ##
@@ s390x/Makefile: tests += $(TEST_DIR)/uv-host.elf
@@ s390x/spec_ex.c (new)
+ */
+static void fixup_invalid_psw(struct stack_frame_int *stack)
+{
++ assert_msg(invalid_psw_expected,
++ "Unexpected invalid PSW during program interrupt fixup: %#lx %#lx",
++ lowcore.pgm_old_psw.mask, lowcore.pgm_old_psw.addr);
+ /* signal occurrence of invalid psw fixup */
+ invalid_psw_expected = false;
+ invalid_psw = lowcore.pgm_old_psw;
@@ s390x/spec_ex.c (new)
+ uint64_t scratch;
+
+ /*
-+ * The fixup psw is current psw with the instruction address replaced by
-+ * the address of the nop following the instruction loading the new psw.
++ * The fixup psw is the current psw with the instruction address replaced
++ * by the address of the nop following the instruction loading the new psw.
+ */
+ fixup_psw.mask = extract_psw_mask();
+ asm volatile ( "larl %[scratch],0f\n"
@@ s390x/spec_ex.c (new)
+
+static int check_invalid_psw(void)
+{
++ /* Since the fixup sets this to false we check for false here. */
+ if (!invalid_psw_expected) {
+ if (expected_psw.mask == invalid_psw.mask &&
+ expected_psw.addr == invalid_psw.addr)
@@ s390x/spec_ex.c (new)
+/* A short PSW needs to have bit 12 set to be valid. */
+static int short_psw_bit_12_is_0(void)
+{
++ struct psw invalid = {
++ .mask = BIT(63 - 12),
++ .addr = 0x00000000deadbeee
++ };
+ struct short_psw short_invalid = {
+ .mask = 0x0,
+ .addr = 0xdeadbeee
+ };
+
++ expect_invalid_psw(invalid);
++ load_short_psw(short_invalid);
+ /*
+ * lpsw may optionally check bit 12 before loading the new psw
+ * -> cannot check the expected invalid psw like with lpswe
+ */
-+ load_short_psw(short_invalid);
+ return 0;
+}
+
2: 0f19be7d ! 2: 697409f7 s390x: Test specification exceptions during transaction
@@ Commit message
Check that we see the expected code for (some) specification exceptions.
Signed-off-by: Janis Schoetterl-Glausch <scgl@xxxxxxxxxxxxx>
+ Reviewed-by: Nico Boehr <nrb@xxxxxxxxxxxxx>
+ Acked-by: Janosch Frank <frankja@xxxxxxxxxxxxx>
## lib/s390x/asm/arch_def.h ##
@@ lib/s390x/asm/arch_def.h: struct cpu {
@@ s390x/spec_ex.c: static int not_even(void)
/*
* Harness for specification exception testing.
* func only triggers exception, reporting is taken care of automatically.
-+ * If a trigger is transactable it will also be executed during a transaction.
++ * If a trigger is transactable it will also be executed during a transaction.
*/
struct spec_ex_trigger {
const char *name;
@@ s390x/spec_ex.c: static void test_spec_ex(const struct spec_ex_trigger *trigger)
+#define TRANSACTION_MAX_RETRIES 5
+
+/*
-+ * NULL must be passed to __builtin_tbegin via constant, forbid diagnose from
-+ * being NULL to keep things simple
++ * NULL must not be passed to __builtin_tbegin via variable, only constant,
++ * forbid diagnose from being NULL at all to keep things simple
+ */
+static int __attribute__((nonnull))
+with_transaction(int (*trigger)(void), struct __htm_tdb *diagnose)
@@ s390x/spec_ex.c: static void test_spec_ex(const struct spec_ex_trigger *trigger)
+
+static void test_spec_ex_trans(struct args *args, const struct spec_ex_trigger *trigger)
+{
-+ const uint16_t expected_pgm = PGM_INT_CODE_SPECIFICATION
-+ | PGM_INT_CODE_TX_ABORTED_EVENT;
++ const uint16_t expected_pgm = PGM_INT_CODE_SPECIFICATION |
++ PGM_INT_CODE_TX_ABORTED_EVENT;
+ union {
+ struct __htm_tdb tdb;
+ uint64_t dwords[sizeof(struct __htm_tdb) / sizeof(uint64_t)];
base-commit: d8a4f9e5e8d69d4ef257b40d6cd666bd2f63494e
--
2.36.1
