Gabriel Paubert <paubert@xxxxxxx> writes: > On Mon, Jul 18, 2022 at 04:31:11PM +1000, Michael Ellerman wrote: >> "Jason A. Donenfeld" <Jason@xxxxxxxxx> writes: >> > The archrandom interface was originally designed for x86, which supplies >> > RDRAND/RDSEED for receiving random words into registers, resulting in >> > one function to generate an int and another to generate a long. However, >> > other architectures don't follow this. >> > >> > On arm64, the SMCCC TRNG interface can return between 1 and 3 words. On >> > s390, the CPACF TRNG interface can return between 1 and 32 words for the >> > same cost as for one word. On UML, the os_getrandom() interface can return >> > arbitrary amounts. >> > >> > So change the api signature to take a "words" parameter designating the >> > maximum number of words requested, and then return the number of words >> > generated. >> >> On powerpc a word is 32-bits and a doubleword is 64-bits (at least >> according to the ISA). I think that's also true on other 64-bit >> architectures. > > IIRC, this is (or was) not the case on Alpha, where word was defined as > 16 bits. All assembly mnemonics had w for 16 bits, l for 32 bits, and q > for 64 bits. Yeah I should have said on *some* other 64-bit arches. Seems to be a common feature/hack on arches that have evolved over time, or been inspired by earlier arches. The latest Power ISA has octwords :) cheers
