On Fri, Jan 21, 2022 at 7:25 AM Guo Ren <guoren@xxxxxxxxxx> wrote: > On Thu, Jan 20, 2022 at 10:43 PM Arnd Bergmann <arnd@xxxxxxxx> wrote: > > On Thu, Jan 20, 2022 at 8:39 AM <guoren@xxxxxxxxxx> wrote: > > Are you sure these are the right calling conventions? According to [1], > > I think the 64-bit argument should be in an aligned pair of registers, > > which means you need an extra pad argument as in the arm64 version > > of these functions. Same for ftruncate64, pread64, pwrite64, and > > readahead. > > [1] has abandoned. > > See: > https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc Ok, thanks for the reference, I picked the first one that came up in a google search and didn't expect this to ever have changed. > > I still feel like these should be the common implementations next to the > > native handlers inside of an #ifdef CONFIG_COMPAT. > > > > The names clash with the custom versions defined for powerpc and sparc, > > but the duplicates look compatible if you can account for the padded > > argument and the lo/hi order of the pairs, so could just be removed here > > (all other architectures use custom function names instead). > I would try it later. This becomes easier then, as powerpc and sparc already have the non-padded calling conventions, so you could just generalize those without looking at the other architectures or adding the padding. The powerpc version already has the dual-endian version, so using that will work on big-endian sparc and on little-endian riscv as well, though we may need to come up with a better name for the arg_u32/arg_u64/merge_64 macros in order to put that into a global header without namespace collisions. Arnd
