Hi, Thomas, > From: Thomas Gleixner <tglx@xxxxxxxxxxxxx> > Sent: Sunday, December 12, 2021 8:12 AM > > Kevin, > > On Sat, Dec 11 2021 at 07:52, Kevin Tian wrote: > >> From: Jason Gunthorpe <jgg@xxxxxxxxxx> > >> > Then Qemu needs to find out the GSI number for the vIRTE handle. > >> > Again Qemu doesn't have such information since it doesn't know > >> > which MSI[-X] entry points to this handle due to no trap. > >> > >> No this is already going wrong. qemu *cannot* know the MSI information > >> because there is no MSI information for IMS. > > > > I haven't thought of IMS at this step. The IR approach applies to > > all types of interrupt storages, thus I'm more interested in how it > > affect the storages which are already virtualized today (MSI[-X] > > in my thought practice). > > They are not any different. As I explained several times now IMS is > nothing new at all. It existed since the invention of Message Signaled > interrupts. Why? > > The principle behind Message Signaled Interrupts is: > > Device writes DATA to ADDRESS which raises an interrupt in a CPU > > Message Signaled Interrupts obviously need some place to store the > ADDRESS/DATA pair so that the device can use it for raising an > interrupt, i.e. an > > Interrupt Message Store, short IMS. > > PCI/MSI was the first implementation of this and the storage was defined > to be at a specified and therefore uniform and device independent place. > > PCI/MSI-X followed the same approch. While it solved quite some of the > shortcomings of PCI/MSI it still has a specificed and uniform and device > independent place to store the message (ADDRESS/DATA pair) > > Now the PCI wizards figured out that PCI/MSI[-X] is not longer up to the > task for various reasons and came up with the revolutionary new concept > of IMS, aka Interrupt Message Store. where the device defines where the > message is stored. > > IOW, this is coming back full circle to the original problem of where to > store the message, i.e. the ADDRESS/DATA pair so that the device can > raise an interrupt in a CPU, which requires - drum roll - an > > Interrupt Message Store, short IMS. > > So you simply have to look at it from a pure MSI (not PCI/MSI) point > of view: > > MSI at the conceptual level requires storage for the ADDRESS/DATA > pair at some place so that the device or the compute unit embedded in > the device can write DATA to ADDRESS. > > That's it. Not more, not less. > > When you look at it from this perspective, then you'll realize that > > PCI/MSI and PCI/MSI-X are just implementations of IMS > > Not more, not less. The fact that they have very strict rules about the > storage space and the fact that they are mutually exclusive does not > change that at all. > > That's where a lot of the confusion comes from. If you go back to all > the IDXD/IMS discussions which happened over time then you'll figure out > that _all_ of us where coming from the same wrong assumption: > > IMS is new and it's just another exclusive variant of PCI/MSI and > PCi/MSI-X. > > It took _all_ of us quite some time to realize that we need to look at > it from the other way around. > > There was surely some other conceptual confusion vs. subdevices, queues > and whatever involved which contributed to that. Water under the bridge. > > Coming back to your initial question: > > > I haven't thought of IMS at this step. The IR approach applies to > > all types of interrupt storages, thus I'm more interested in how it > > affect the storages which are already virtualized today (MSI[-X] > > in my thought practice). > > Stop focussing on implementation details. Focus on the general concept > instead. See above. > I have no any problem on understanding above relational. This has been acked multiple times in my previous replies. I just continue the thought practice along that direction to see what the host flow will be like (step by step). Looking at the current implementation is just one necessary step in my thought practice to help refine the picture. When I found something which may be worth being aligned then I shared to avoid follow a wrong direction too far. If both of your think it simply adds noise to this discussion, I can surely hold back and focus on 'concept' only. Thanks Kevin
