On a diag308 subcode 0 CRs will be reset, so we need a PSW mask
without DAT. Also we need to set the short psw indication to be
compliant with the architecture.
Let's therefore define a reset PSW mask with 64 bit addressing and
short PSW indication that is compliant with architecture and use it.
Signed-off-by: Janosch Frank <frankja@xxxxxxxxxxxxx>
---
lib/s390x/asm-offsets.c | 1 +
lib/s390x/asm/arch_def.h | 3 ++-
s390x/cstart64.S | 24 +++++++++++++++++-------
3 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/lib/s390x/asm-offsets.c b/lib/s390x/asm-offsets.c
index 4b213f8..61d2658 100644
--- a/lib/s390x/asm-offsets.c
+++ b/lib/s390x/asm-offsets.c
@@ -58,6 +58,7 @@ int main(void)
OFFSET(GEN_LC_SW_INT_FPRS, lowcore, sw_int_fprs);
OFFSET(GEN_LC_SW_INT_FPC, lowcore, sw_int_fpc);
OFFSET(GEN_LC_SW_INT_CRS, lowcore, sw_int_crs);
+ OFFSET(GEN_LC_SW_INT_PSW, lowcore, sw_int_psw);
OFFSET(GEN_LC_MCCK_EXT_SA_ADDR, lowcore, mcck_ext_sa_addr);
OFFSET(GEN_LC_FPRS_SA, lowcore, fprs_sa);
OFFSET(GEN_LC_GRS_SA, lowcore, grs_sa);
diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h
index 07d4e5e..7d25e4f 100644
--- a/lib/s390x/asm/arch_def.h
+++ b/lib/s390x/asm/arch_def.h
@@ -79,7 +79,8 @@ struct lowcore {
uint32_t sw_int_fpc; /* 0x0300 */
uint8_t pad_0x0304[0x0308 - 0x0304]; /* 0x0304 */
uint64_t sw_int_crs[16]; /* 0x0308 */
- uint8_t pad_0x0310[0x11b0 - 0x0388]; /* 0x0388 */
+ struct psw sw_int_psw; /* 0x0388 */
+ uint8_t pad_0x0310[0x11b0 - 0x0390]; /* 0x0390 */
uint64_t mcck_ext_sa_addr; /* 0x11b0 */
uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */
uint64_t fprs_sa[16]; /* 0x1200 */
diff --git a/s390x/cstart64.S b/s390x/cstart64.S
index 4be20fc..86dd4c4 100644
--- a/s390x/cstart64.S
+++ b/s390x/cstart64.S
@@ -126,13 +126,18 @@ memsetxc:
.globl diag308_load_reset
diag308_load_reset:
SAVE_REGS
- /* Save the first PSW word to the IPL PSW */
+ /* Backup current PSW mask, as we have to restore it on success */
epsw %r0, %r1
- st %r0, 0
- /* Store the address and the bit for 31 bit addressing */
- larl %r0, 0f
- oilh %r0, 0x8000
- st %r0, 0x4
+ st %r0, GEN_LC_SW_INT_PSW
+ st %r1, GEN_LC_SW_INT_PSW + 4
+ /* Load reset psw mask (short psw, 64 bit) */
+ lg %r0, reset_psw
+ /* Load the success label address */
+ larl %r1, 0f
+ /* Or it to the mask */
+ ogr %r0, %r1
+ /* Store it at the reset PSW location (real 0x0) */
+ stg %r0, 0
/* Do the reset */
diag %r0,%r2,0x308
/* Failure path */
@@ -144,7 +149,10 @@ diag308_load_reset:
lctlg %c0, %c0, 0(%r1)
RESTORE_REGS
lhi %r2, 1
- br %r14
+ larl %r0, 1f
+ stg %r0, GEN_LC_SW_INT_PSW + 8
+ lpswe GEN_LC_SW_INT_PSW
+1: br %r14
.globl smp_cpu_setup_state
smp_cpu_setup_state:
@@ -184,6 +192,8 @@ svc_int:
lpswe GEN_LC_SVC_OLD_PSW
.align 8
+reset_psw:
+ .quad 0x0008000180000000
initial_psw:
.quad 0x0000000180000000, clear_bss_start
pgm_int_psw:
--
2.20.1
