On 05.11.19 19:04, Cornelia Huck wrote: > On Thu, 24 Oct 2019 07:40:34 -0400 > Janosch Frank <frankja@xxxxxxxxxxxxx> wrote: > >> Since KVM doesn't emulate any form of load control and load psw >> instructions anymore, we wouldn't get an interception if PSWs or CRs >> are changed in the guest. That means we can't inject IRQs right after >> the guest is enabled for them. >> >> The new interception codes solve that problem by being a notification >> for changes to IRQ enablement relevant bits in CRs 0, 6 and 14, as >> well a the machine check mask bit in the PSW. >> >> No special handling is needed for these interception codes, the KVM >> pre-run code will consult all necessary CRs and PSW bits and inject >> IRQs the guest is enabled for. > > Just to clarify: The hypervisor can still access the relevant bits for > pv guests, this is only about the notification, right? > Yes, the hypervisor (KVM) can always read the relevant PSW bits (I,E,M) and CR bits to decide if an interrupt can be delivered. All other bits of PSW and CRx are masked though. This is a new intercept for notification as we do no longer get an IC4 (instruction to handle) for load control and friends so that we can re-check the bits. >> >> Signed-off-by: Janosch Frank <frankja@xxxxxxxxxxxxx> >> --- >> arch/s390/include/asm/kvm_host.h | 2 ++ >> arch/s390/kvm/intercept.c | 18 ++++++++++++++++++ >> 2 files changed, 20 insertions(+) >
