Re: [RFC 12/37] KVM: s390: protvirt: Handle SE notification interceptions

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On 10/30/19 4:50 PM, David Hildenbrand wrote:
> On 24.10.19 13:40, Janosch Frank wrote:
>> Since KVM doesn't emulate any form of load control and load psw
>> instructions anymore, we wouldn't get an interception if PSWs or CRs
>> are changed in the guest. That means we can't inject IRQs right after
>> the guest is enabled for them.
>>
>> The new interception codes solve that problem by being a notification
>> for changes to IRQ enablement relevant bits in CRs 0, 6 and 14, as
>> well a the machine check mask bit in the PSW.
>>
>> No special handling is needed for these interception codes, the KVM
>> pre-run code will consult all necessary CRs and PSW bits and inject
>> IRQs the guest is enabled for.
>>
>> Signed-off-by: Janosch Frank <frankja@xxxxxxxxxxxxx>
>> ---
>>   arch/s390/include/asm/kvm_host.h |  2 ++
>>   arch/s390/kvm/intercept.c        | 18 ++++++++++++++++++
>>   2 files changed, 20 insertions(+)
>>
>> diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h
>> index d4fd0f3af676..6cc3b73ca904 100644
>> --- a/arch/s390/include/asm/kvm_host.h
>> +++ b/arch/s390/include/asm/kvm_host.h
>> @@ -210,6 +210,8 @@ struct kvm_s390_sie_block {
>>   #define ICPT_PARTEXEC	0x38
>>   #define ICPT_IOINST	0x40
>>   #define ICPT_KSS	0x5c
>> +#define ICPT_PV_MCHKR	0x60
>> +#define ICPT_PV_INT_EN	0x64
>>   	__u8	icptcode;		/* 0x0050 */
>>   	__u8	icptstatus;		/* 0x0051 */
>>   	__u16	ihcpu;			/* 0x0052 */
>> diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c
>> index a389fa85cca2..acc1710fc472 100644
>> --- a/arch/s390/kvm/intercept.c
>> +++ b/arch/s390/kvm/intercept.c
>> @@ -480,6 +480,24 @@ int kvm_handle_sie_intercept(struct kvm_vcpu *vcpu)
>>   	case ICPT_KSS:
>>   		rc = kvm_s390_skey_check_enable(vcpu);
>>   		break;
>> +	case ICPT_PV_MCHKR:
>> +		/*
>> +		 * A protected guest changed PSW bit 13 to one and is now
>> +		 * enabled for interrupts. The pre-run code will check
>> +		 * the registers and inject pending MCHKs based on the
>> +		 * PSW and CRs. No additional work to do.
>> +		 */
>> +		rc = 0;
>> +		break;
>> +	case  ICPT_PV_INT_EN:
>> +		/*
>> +		 * A protected guest changed CR 0,6,14 and may now be
>> +		 * enabled for interrupts. The pre-run code will check
>> +		 * the registers and inject pending IRQs based on the
>> +		 * CRs. No additional work to do.
>> +		 */
>> +		rc = 0;
>> +	break;
> 
> Wrong indentation.
> 
> Maybe simply
> 
> case ICPT_PV_MCHKR:
> ICPT_PV_INT_EN:
> 	/*
> 	 * PSW bit 13 or a CR (0, 6, 14) changed and we might now be
>           * able to deliver interrupts. pre-run code will take care of
>           * this.
> 	 */
> 	rc = 0;
> 	break;

Sounds good, I'll fix it


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