On 31.10.18 13:45, Cornelia Huck wrote:
On Thu, 25 Oct 2018 14:37:50 +0200
Michael Mueller <mimu@xxxxxxxxxxxxx> wrote:
The patch implements a handler for GIB alert interruptions
on the host. Its task is to alert storage backed guests that
interrupts are pending for them.
A GIB alert interrupt statistic counter is added as well:
$ cat /proc/interrupts
CPU0 CPU1
...
GAL: 0 0 [I/O] GIB Alert
...
Signed-off-by: Michael Mueller <mimu@xxxxxxxxxxxxx>
---
arch/s390/include/asm/irq.h | 1 +
arch/s390/include/asm/isc.h | 1 +
arch/s390/kernel/irq.c | 1 +
arch/s390/kvm/interrupt.c | 45 +++++++++++++++++++++++++++++++++----
arch/s390/kvm/kvm-s390.c | 5 +++++
5 files changed, 49 insertions(+), 4 deletions(-)
diff --git a/arch/s390/include/asm/irq.h b/arch/s390/include/asm/irq.h
index 2f7f27e5493f..afaf5e3c57fd 100644
--- a/arch/s390/include/asm/irq.h
+++ b/arch/s390/include/asm/irq.h
@@ -62,6 +62,7 @@ enum interruption_class {
IRQIO_MSI,
IRQIO_VIR,
IRQIO_VAI,
+ IRQIO_GAL,
NMI_NMI,
CPU_RST,
NR_ARCH_IRQS
diff --git a/arch/s390/include/asm/isc.h b/arch/s390/include/asm/isc.h
index 6cb9e2ed05b6..b2cc1ec78d06 100644
--- a/arch/s390/include/asm/isc.h
+++ b/arch/s390/include/asm/isc.h
@@ -21,6 +21,7 @@
/* Adapter interrupts. */
#define QDIO_AIRQ_ISC IO_SCH_ISC /* I/O subchannel in qdio mode */
#define PCI_ISC 2 /* PCI I/O subchannels */
+#define GAL_ISC 5 /* GIB alert */
Dumb question: iscs are ordered by priority. What are the semantics
here? Are gib alerts only for ap-style adapter interrupts (at least
currently, it seems to me like that)? Is there a requirement to use a
distinct isc?
GIB alerts will be issued for all sorts of passed-trough adapters. Currently
we are looking for AP and later for PCI as well. The GIB alert is a
*fallback
mechanism* when the interruption cannot be directly delivered in-sie.
Thus I consider its priority as less important.
Why a distinct ISC? That is probably not required. On the other hand I don't
want to trigger the GAL handler by adapter interruptions for other reasons.
#define AP_ISC 6 /* adjunct processor (crypto) devices */
/* Functions for registration of I/O interruption subclasses */
--
Mit freundlichen Grüßen / Kind regards
Michael Müller
IBM Deutschland Research & Development GmbH
Vorsitzender des Aufsichtsrats: Martina Köderitz
Geschäftsführung: Dirk Wittkopp
Sitz der Gesellschaft: Böblingen
Registergericht: Amtsgericht Stuttgart, HRB 243294
