From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
Add the DT node for the VBATTB IP along with DT bindings for the clock
it provides.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 32 ++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 2162c247d6de..b7bd2e1f3462 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -72,6 +72,31 @@ scif0: serial@1004b800 {
status = "disabled";
};
+ vbattb: vbattb@1005c000 {
+ compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd";
+ reg = <0 0x1005c000 0 0x1000>;
+ ranges = <0 0 0 0x1005c000 0 0x1000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tampdi";
+ clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>;
+ clock-names = "bclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_VBAT_BRESETN>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ vbattclk: clock-controller@1c {
+ compatible = "renesas,rzg3s-vbattb-clk";
+ reg = <0 0x1c 0 0x10>;
+ clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
+ clock-names = "bclk", "vbattb_xtal";
+ #clock-cells = <0>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+ };
+
cpg: clock-controller@11010000 {
compatible = "renesas,r9a08g045-cpg";
reg = <0 0x11010000 0 0x10000>;
@@ -296,4 +321,11 @@ timer {
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
+
+ vbattb_xtal: vbattb-xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
};
--
2.39.2
