PCF2127/29/31 is capable of generating an interrupt on every
second (SI) or minute (MI) change. It signals this through
the Minute/Second Flag (MSF) as well, which needs to be cleared.
Co-developed-by: "Szentendrei, Tamás" <szentendrei.tamas@xxxxxxxxx>
Signed-off-by: "Szentendrei, Tamás" <szentendrei.tamas@xxxxxxxxx>
Signed-off-by: "Csókás, Bence" <csokas.bence@xxxxxxxxx>
---
drivers/rtc/rtc-pcf2127.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index 9c04c4e1a49c..7efff014a58d 100644
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -31,6 +31,10 @@
/* Control register 1 */
#define PCF2127_REG_CTRL1 0x00
+/* Change interrupt. 1=seconds change, 2=minutes */
+#define PCF2127_CTRL1_MSI_MASK GENMASK(1, 0)
+#define PCF2127_BIT_CTRL1_SI BIT(0)
+#define PCF2127_BIT_CTRL1_MI BIT(1)
#define PCF2127_BIT_CTRL1_POR_OVRD BIT(3)
#define PCF2127_BIT_CTRL1_TSF1 BIT(4)
#define PCF2127_BIT_CTRL1_STOP BIT(5)
@@ -41,6 +45,7 @@
#define PCF2127_BIT_CTRL2_AF BIT(4)
#define PCF2127_BIT_CTRL2_TSF2 BIT(5)
#define PCF2127_BIT_CTRL2_WDTF BIT(6)
+#define PCF2127_BIT_CTRL2_MSF BIT(7)
/* Control register 3 */
#define PCF2127_REG_CTRL3 0x02
#define PCF2127_BIT_CTRL3_BLIE BIT(0)
@@ -92,6 +97,7 @@
/* Mask for currently enabled interrupts */
#define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1)
#define PCF2127_CTRL2_IRQ_MASK ( \
+ PCF2127_CTRL1_MSI_MASK | \
PCF2127_BIT_CTRL2_AF | \
PCF2127_BIT_CTRL2_WDTF | \
PCF2127_BIT_CTRL2_TSF2)
@@ -143,6 +149,7 @@
#define PCF2131_BIT_INT_SI BIT(4)
#define PCF2131_BIT_INT_MI BIT(5)
#define PCF2131_CTRL2_IRQ_MASK ( \
+ PCF2127_CTRL1_MSI_MASK | \
PCF2127_BIT_CTRL2_AF | \
PCF2127_BIT_CTRL2_WDTF)
#define PCF2131_CTRL4_IRQ_MASK ( \
@@ -604,6 +611,20 @@ static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled);
}
+static int pcf2127_rtc_update_irq_enable(struct device *dev, u32 enable)
+{
+ struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
+ int ret;
+
+ ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
+ PCF2127_CTRL1_MSI_MASK,
+ enable ? PCF2127_BIT_CTRL1_SI : 0);
+ if (ret)
+ return ret;
+
+ return pcf2127_wdt_active_ping(&pcf2127->wdd);
+}
+
/*
* This function reads one timestamp function data, caller is responsible for
* calling pcf2127_wdt_active_ping()
@@ -728,6 +749,8 @@ static irqreturn_t pcf2127_rtc_irq(int irq, void *dev)
if (ctrl2 & PCF2127_BIT_CTRL2_AF)
rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF);
+ else if (ctrl2 & PCF2127_BIT_CTRL2_MSF)
+ rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_UF);
pcf2127_wdt_active_ping(&pcf2127->wdd);
@@ -741,6 +764,7 @@ static const struct rtc_class_ops pcf2127_rtc_ops = {
.read_alarm = pcf2127_rtc_read_alarm,
.set_alarm = pcf2127_rtc_set_alarm,
.alarm_irq_enable = pcf2127_rtc_alarm_irq_enable,
+ .update_irq_enable = pcf2127_rtc_update_irq_enable,
};
/* sysfs interface */
--
2.34.1
