On 12/04/2022 20:29, Conor Dooley wrote: > The way it's implemented is a bit interconnected and none of the three > blocks would satisfy a "self contained" constraint. Eg. The rtcref > divider's control reg sits between two registers responsible for the > CLK_CPU -> CLK_CFM clocks but it's input clock mux is in the same > sub-block as the MSSPLL. > > I guess its better put that each of the three are sub-blocks of a self > contained clock controller for the mss core complex. There are several > other clock domains on the chip which would have distinct clock > controllers & may be added to this header in the future, if letting > Linux control them makes any sense. For example, clocks in (and used for > the clocking of) the fpga fabric. > > This controller is a single node in the device tree. Sounds like > reordering it numerically makes the most sense then - I'll resend > tomorrow if that's okay. Yes. Best regards, Krzysztof
