On 08/04/2022 16:36, Conor Dooley wrote: > As there are two sections of registers that are responsible for clock > configuration on the PolarFire SoC: add the dynamic reconfiguration > interface section to the binding & describe what each of the sections > are used for. (...) > > reg: > - maxItems: 1 > + items: > + - description: | > + clock config registers: > + These registers contain enable, reset & divider tables for the, cpu, axi, ahb and > + rtc/mtimer reference clocks as well as enable and reset for the peripheral clocks. > + - description: | > + mss pll dri registers: > + Block of registers responsible for dynamic reconfiguration of the mss pll > This breaks all of DTS - in and out of tree. Best regards, Krzysztof
