On Fri, Nov 27, 2020 at 08:11:05AM +0100, Uwe Kleine-König wrote:
> Hello Jonathan,
>
> On Fri, Nov 27, 2020 at 12:19:31AM +0100, Jonathan Neuschäfer wrote:
> > On Tue, Nov 24, 2020 at 09:20:19AM +0100, Uwe Kleine-König wrote:
[...]
> > > state->duty_cycle and state->period are u64, so you're losing
> > > information here. Consider state->duty_cycle = 0x100000001 and
> > > state->period = 0x200000001.
> >
> > Oh, good point, I didn't notice the truncation.
> >
> > The reason I picked unsigned int was to avoid a 64-bit division;
> > I suppose I can do something like this:
> >
> > period = (u32)period / TIME_BASE_NS;
> > duty = (u32)duty / TIME_BASE_NS;
>
> You can do that after you checked period > MAX_PERIOD_NS below, yes.
> Something like:
>
> if (state->polarity != PWM_POLARITY_NORMAL)
> return -EINVAL;
>
> if (state->period > MAX_PERIOD_NS) {
> period = MAX_PERIOD_NS;
> else
> period = state->period;
>
> if (state->duty_cycle > period)
> duty_cycle = period;
> else
> duty_cycle = state->duty_cycle;
>
> should work with even keeping the local variables as unsigned int.
With the min_t() macro, this becomes nice and short:
period = min_t(u64, state->period, MAX_PERIOD_NS);
duty = min_t(u64, state->duty_cycle, period);
period /= TIME_BASE_NS;
duty /= TIME_BASE_NS;
> > > I think I already asked, but I don't remember the reply: What happens to
> > > the output between these writes? A comment here about this would be
> > > suitable.
> >
> > I will add something like the following:
> >
> > /*
> > * Changes to the period and duty cycle take effect as soon as the
> > * corresponding low byte is written, so the hardware may be configured
> > * to an inconsistent state after the period is written and before the
> > * duty cycle is fully written. If, in such a case, the old duty cycle
> > * is longer than the new period, the EC will output 100% for a moment.
> > */
>
> Is the value pair taken over by hardware atomically? That is, is it
> really "will" in your last line, or only "might". (E.g. when changing
> from duty_cycle, period = 1000, 2000 to 500, 800 and a new cycle begins
> after reducing period, the new duty_cycle is probably written before the
> counter reaches 500. Do we get a 100% cycle here?)
I am not sure when exactly a new period or duty cycle value is applied,
and I don't have the test equipment to measure it. I'll change the text
to "may output 100%".
> Other than that the info is fine. Make sure to point this out in the
> Limitations paragraph at the top of the driver please, too.
Okay.
> > > /*
> > > * The current state cannot be read out, so there is no .get_state
> > > * callback.
> > > */
> > >
> > > Hmm, at least you could provice a .get_state() callback that reports the
> > > setting that was actually implemented for in the last call to .apply()?
> >
> > Yes... I see two options:
> >
> > 1. Caching the state in the driver's private struct. I'm not completely
> > convinced of the value, given that the information is mostly
> > available in the PWM core already (except for the adjustments that
> > the driver makes).
> >
> > 2. Writing the adjusted state back into pwm_dev->state (via pwm_set_*).
> > This seems a bit dirty.
>
> 2. isn't a good option. Maybe regmap caches this stuff anyhow for 1. (or
> can be made doing that)?
With regmap caching, I'd be concerned that a read operation may slip
through and reach the device, producing a bogus result. Not sure if
write-only/write-through caching can be configured in regmap.
Thanks,
Jonathan
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