On Sat, 23 May 2020, Ivan Kokshaysky wrote: > On Sat, May 23, 2020 at 06:26:54AM -0400, Mikulas Patocka wrote: > > The commits cd0e00c10672 and 92d7223a7423 broke boot on the Alpha Avanti > > platform. The patches move memory barriers after a write before the write. > > The result is that if there's iowrite followed by ioread, there is no > > barrier between them. > > > > The Alpha architecture allows reordering of the accesses to the I/O space, > > and the missing barrier between write and read causes hang with serial > > port and real time clock. > > > > This patch makes barriers confiorm to the specification. > > > > 1. We add mb() before readX_relaxed and writeX_relaxed - > > memory-barriers.txt claims that these functions must be ordered w.r.t. > > each other. Alpha doesn't order them, so we need an explicit barrier. > > 2. We add mb() before reads from the I/O space - so that if there's a > > write followed by a read, there should be a barrier between them. > > You missed the second mb() in extern inline u16 readw(). Otherwise, > > Acked-by: Ivan Kokshaysky <ink@xxxxxxxxxxxxxxxxxxxx> ... and I also broke the *_relaxed macros and didn't notice it, because they are unused in my config. This won't compile, because mb() is a statement, not a function. > > +#define readb_relaxed(addr) (mb(), __raw_readb(addr)) I'll send a new version of the patch. Mikulas
