>> So I confirmed that atomic operations from >> arch/arm64/include/asm/atomic_ll_sc.h can be quite slow when they are >> contested from second CPU. >> >> Do you think that it is possible to create fair qspinlock implementation >> on top of atomic instructions supported by ARM64 version 8 (no LSE atomic >> instructions) without compromising performance in the uncontested case? >> For example ARM64 could have custom queued_fetch_set_pending_acquire >> implementation same as x86 has in arch/x86/include/asm/qspinlock.h. Is the >> retry loop in irq_finalize_oneshot() ok together with the current ARM64 >> cpu_relax() implementation for processor with no LSE atomic instructions? > >So is the queued_fetch_set_pending_acquire() where it gets stuck or the >earlier atomic_try_cmpxchg_acquire() before entering on the slow path? I >guess both can fail in a similar way. For me it was stuck on queued_fetch_set_pending_acquire(). Zdenek Bouska -- Siemens, s.r.o Siemens Advanta Development
