Re: [PATCH v2] rt-tests: resync has_smi_counter with turbostat code

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John,

Sorry for the trouble - this was my first time submitting a patch to a
mailing list.

I (stupidly) thought I could just generate the patch with "git
format-patch" and then cut/paste it into a text format email.
Unfortunately, gmail decided to insert line breaks and convert the
tabs to spaces, which explains why it won't apply for you.

And yes - the patch was generated against main - not on top of your
original patch.

I will figure out how to submit this with "git send-email" and upload
v3 of the patch for you to review.

Thanks,
Bart

On Tue, Apr 12, 2022 at 2:50 PM John Kacur <jkacur@xxxxxxxxxx> wrote:
>
>
>
> On Mon, 11 Apr 2022, Bart Wensley wrote:
>
> > Updating has_smi_counter to match most recent turbostat code, in
> > order to support recent cpu models (e.g. Ice Lake).
> >
> > Restructured the code to match the turbostat functions so it will
> > be easier to keep the code in sync in the future.
> >
> > Signed-off-by: bartwensley <bwensley@xxxxxxxxxx>
> > ---
> >  src/cyclictest/cyclictest.c | 104 +++++++++++++++++++++++++-----------
> >  1 file changed, 73 insertions(+), 31 deletions(-)
> >
> > diff --git a/src/cyclictest/cyclictest.c b/src/cyclictest/cyclictest.c
> > index c9ed9e0..da430dc 100644
> > --- a/src/cyclictest/cyclictest.c
> > +++ b/src/cyclictest/cyclictest.c
> > @@ -432,39 +432,81 @@ static int has_smi_counter(void)
> >
> >         model = (((fms >> 16) & 0xf) << 4) + ((fms >> 4) & 0xf);
> >
> > +       /* Based on intel_model_duplicates */
> >         switch (model) {
> > -       case 0x1A:      /* Core i7, Xeon 5500 series - Bloomfield,
> > Gainstown NHM-EP */
> > -       case 0x1E:      /* Core i7 and i5 Processor - Clarksfield,
> > Lynnfield, Jasper Forest */
> > +       case 0x1A:      /* INTEL_FAM6_NEHALEM_EP */
> > +       case 0x1E:      /* INTEL_FAM6_NEHALEM */
> >         case 0x1F:      /* Core i7 and i5 Processor - Nehalem */
> > -       case 0x25:      /* Westmere Client - Clarkdale, Arrandale */
> > -       case 0x2C:      /* Westmere EP - Gulftown */
> > -       case 0x2E:      /* Nehalem-EX Xeon - Beckton */
> > -       case 0x2F:      /* Westmere-EX Xeon - Eagleton */
> > -       case 0x2A:      /* SNB */
> > -       case 0x2D:      /* SNB Xeon */
> > -       case 0x3A:      /* IVB */
> > -       case 0x3E:      /* IVB Xeon */
> > -       case 0x3C:      /* HSW */
> > -       case 0x3F:      /* HSX */
> > -       case 0x45:      /* HSW */
> > -       case 0x46:      /* HSW */
> > -       case 0x3D:      /* BDW */
> > -       case 0x47:      /* BDW */
> > -       case 0x4F:      /* BDX */
> > -       case 0x56:      /* BDX-DE */
> > -       case 0x4E:      /* SKL */
> > -       case 0x5E:      /* SKL */
> > -       case 0x8E:      /* KBL */
> > -       case 0x9E:      /* KBL */
> > -       case 0x55:      /* SKX */
> > -       case 0x37:      /* BYT */
> > -       case 0x4D:      /* AVN */
> > -       case 0x4C:      /* AMT */
> > -       case 0x57:      /* PHI */
> > -       case 0x5C:      /* BXT */
> > -       case 0x5F:      /* DNV */
> > -       case 0x7A:      /* Gemini Lake */
> > -       case 0x85:      /* Knights Mill */
> > +       case 0x25:      /* INTEL_FAM6_WESTMERE */
> > +       case 0x2C:      /* INTEL_FAM6_WESTMERE_EP */
> > +               model = 0x1E;      /* INTEL_FAM6_NEHALEM */
> > +               break;
> > +       case 0x2E:      /* INTEL_FAM6_NEHALEM_EX */
> > +       case 0x2F:      /* INTEL_FAM6_WESTMERE_EX */
> > +               model = 0x2E;      /* INTEL_FAM6_NEHALEM_EX */
> > +               break;
> > +       case 0x85:      /* INTEL_FAM6_XEON_PHI_KNM */
> > +               model = 0x57;      /* INTEL_FAM6_XEON_PHI_KNL */
> > +               break;
> > +       case 0x4F:      /* INTEL_FAM6_BROADWELL_X */
> > +       case 0x56:      /* INTEL_FAM6_BROADWELL_D */
> > +               model = 0x4F;      /* INTEL_FAM6_BROADWELL_X */
> > +               break;
> > +       case 0x4E:      /* INTEL_FAM6_SKYLAKE_L */
> > +       case 0x5E:      /* INTEL_FAM6_SKYLAKE */
> > +       case 0x8E:      /* INTEL_FAM6_KABYLAKE_L */
> > +       case 0x9E:      /* INTEL_FAM6_KABYLAKE */
> > +       case 0xA6:      /* INTEL_FAM6_COMETLAKE_L */
> > +       case 0xA5:      /* INTEL_FAM6_COMETLAKE */
> > +               model = 0x4E;      /* INTEL_FAM6_SKYLAKE_L */
> > +               break;
> > +       case 0x7E:      /* INTEL_FAM6_ICELAKE_L */
> > +       case 0x9D:      /* INTEL_FAM6_ICELAKE_NNPI */
> > +       case 0x8C:      /* INTEL_FAM6_TIGERLAKE_L */
> > +       case 0x8D:      /* INTEL_FAM6_TIGERLAKE */
> > +       case 0xA7:      /* INTEL_FAM6_ROCKETLAKE */
> > +       case 0x8A:      /* INTEL_FAM6_LAKEFIELD */
> > +       case 0x97:      /* INTEL_FAM6_ALDERLAKE */
> > +       case 0x9A:      /* INTEL_FAM6_ALDERLAKE_L */
> > +               model = 0x66;      /* INTEL_FAM6_CANNONLAKE_L */
> > +               break;
> > +       case 0x9C:      /* INTEL_FAM6_ATOM_TREMONT_L */
> > +               model = 0x96;      /* INTEL_FAM6_ATOM_TREMONT */
> > +               break;
> > +       case 0x6C:      /* INTEL_FAM6_ICELAKE_D */
> > +       case 0x8F:      /* INTEL_FAM6_SAPPHIRERAPIDS_X */
> > +               model = 0x6A;      /* INTEL_FAM6_ICELAKE_X */
> > +               break;
> > +       }
> > +
> > +       /* Based on probe_nhm_msrs */
> > +       switch (model) {
> > +       case 0x1E:      /* INTEL_FAM6_NEHALEM */
> > +       case 0x2E:      /* INTEL_FAM6_NEHALEM_EX */
> > +       case 0x2A:      /* INTEL_FAM6_SANDYBRIDGE */
> > +       case 0x2D:      /* INTEL_FAM6_SANDYBRIDGE_X */
> > +       case 0x3A:      /* INTEL_FAM6_IVYBRIDGE */
> > +       case 0x3E:      /* INTEL_FAM6_IVYBRIDGE_X */
> > +       case 0x3C:      /* INTEL_FAM6_HASWELL */
> > +       case 0x46:      /* INTEL_FAM6_HASWELL_G */
> > +       case 0x3F:      /* INTEL_FAM6_HASWELL_X */
> > +       case 0x45:      /* INTEL_FAM6_HASWELL_L */
> > +       case 0x3D:      /* INTEL_FAM6_BROADWELL */
> > +       case 0x47:      /* INTEL_FAM6_BROADWELL_G */
> > +       case 0x4F:      /* INTEL_FAM6_BROADWELL_X */
> > +       case 0x4E:      /* INTEL_FAM6_SKYLAKE_L */
> > +       case 0x66:      /* INTEL_FAM6_CANNONLAKE_L */
> > +       case 0x55:      /* INTEL_FAM6_SKYLAKE_X */
> > +       case 0x6A:      /* INTEL_FAM6_ICELAKE_X */
> > +       case 0x37:      /* INTEL_FAM6_ATOM_SILVERMONT */
> > +       case 0x4D:      /* INTEL_FAM6_ATOM_SILVERMONT_D */
> > +       case 0x4C:      /* INTEL_FAM6_ATOM_AIRMONT */
> > +       case 0x57:      /* INTEL_FAM6_XEON_PHI_KNL */
> > +       case 0x5C:      /* INTEL_FAM6_ATOM_GOLDMONT */
> > +       case 0x7A:      /* INTEL_FAM6_ATOM_GOLDMONT_PLUS */
> > +       case 0x5F:      /* INTEL_FAM6_ATOM_GOLDMONT_D */
> > +       case 0x96:      /* INTEL_FAM6_ATOM_TREMONT */
> > +       case 0x86:      /* INTEL_FAM6_ATOM_TREMONT_D */
> >                 break;
> >         default:
> >                 return 0;
> > --
> > 2.35.1
>
> Ok, thanks for working on this, but there are a couple of problems here.
>
> I assume that this patch is against main, and doesn't include the patch I
> already posted, it would be good to let me know. (yes I can figure it out,
> but still)
>
> Also this patch does not apply cleanly. Not sure if this is due to style
> problems or something else. You are getting source from some variation of
> git://git.kernel.org/pub/scm/utils/rt-tests/rt-tests.git
> correct?
>
> Could you run checkpatch.pl from the kernel on this?
> When I run checkpatch on it I get 17 errors and 71 warnings
> Even your signed-off-by seems incorrect.
>
> So please fix all the problems and send a version 3, and then I will
> review it.
>
> Thanks
>
> John
>
>




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