RE: cyclictest result variations

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Hi Luis,

On 29 March 2018 14:54, Luis Claudio R. Goncalves wrote:
> On Thu, Mar 29, 2018 at 07:30:27AM +0000, Phil Edworthy wrote:
> > Hi John, Clark,
> >
> > On 28 March 2018 16:32, Clark Williams wrote:
> > > On Wed, 28 Mar 2018 16:56:27 +0200
> > > John Ogness <john.ogness@xxxxxxxxxxxxx> wrote:
> > >
> > > > On 2018-03-28, Phil Edworthy <phil.edworthy@xxxxxxxxxxx> wrote:
> > > > >> > I found that cyclictest results vary from one run to another.
[...]
> > I did some overnight tests with 100 runs of cyclictest running for 1 minute.
> > Stats below were calculated using stats package from
> > http://web.cs.wpi.edu/~claypool/misc/stats/stats.html
> >
> > 1. Interval fixed to 400us, not using --secalign
> > Min: 20  Avg: 37  Max: 187  (avg of 100xMax is 134)
> >
> > 2. Interval fixed to 400us, using --secalign
> > Min: 20  Avg: 37  Max: 177  (avg of 100xMax is 150)
> >
> > 3. Interval increases from 400 to 499, not using --secalign
> > Min: 20  Avg: 37  Max: 211  (avg of 100xMax is 157)
> >
> > 4. Interval increases from 400 to 499, using --secalign
> > Min: 20  Avg: 37  Max: 202  (avg of 100xMax is 157)
> >
> > While --secalign may provide more consistent results, it appears that
> > it is not as good at identifying the worst case latency.
> > It appears that testing different intervals is much better at
> > identifying the worst case latency.
> 
> Have you used the hwlat ftrace tracer or hwlatdetector.py from rt-tests in
> order to verify if your system have SMI-induced latency spikes? That may not
> be part of the problem described here, but spurious SMI spikes could
> account to some of the discrepancies.
This is on ARM, so no SMI. There's no BIOS, nothing like that.

Thanks
Phil
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