Hi
Am Donnerstag, 4. Januar 2018, 11:24:37 CET schrieben Sie:
> On Thu, Jan 4, 2018 at 10:29 AM, Hindman, Gavin <gavin.hindman@xxxxxxxxx> wrote:
> For ARM platforms, we've found turning off power management helps.
> The book-keeping was costing a lot of time in latency critical spots.
Its not only the book-keeping. I also patched out wfi on i.mx3x since waking
up from sleeping took some considerable delays. But that depends on your latency
requirements and your actual cpu.
The patch below is for an older 3.4.x kernel as example for further tuning power vs. latency.
Best regards
Tim
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 7412738..7b3d312 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -33,33 +33,6 @@
static void imx3_idle(void)
{
- unsigned long reg = 0;
-
- mx3_cpu_lp_set(MX3_WAIT);
-
- __asm__ __volatile__(
- /* disable I and D cache */
- "mrc p15, 0, %0, c1, c0, 0\n"
- "bic %0, %0, #0x00001000\n"
- "bic %0, %0, #0x00000004\n"
- "mcr p15, 0, %0, c1, c0, 0\n"
- /* invalidate I cache */
- "mov %0, #0\n"
- "mcr p15, 0, %0, c7, c5, 0\n"
- /* clear and invalidate D cache */
- "mov %0, #0\n"
- "mcr p15, 0, %0, c7, c14, 0\n"
- /* WFI */
- "mov %0, #0\n"
- "mcr p15, 0, %0, c7, c0, 4\n"
- "nop\n" "nop\n" "nop\n" "nop\n"
- "nop\n" "nop\n" "nop\n"
- /* enable I and D cache */
- "mrc p15, 0, %0, c1, c0, 0\n"
- "orr %0, %0, #0x00001000\n"
- "orr %0, %0, #0x00000004\n"
- "mcr p15, 0, %0, c1, c0, 0\n"
- : "=r" (reg));
}
static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
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