On Tue, 2 Oct 2007 00:47:12 +0200 (CEST) Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote: > On Tue, 2 Oct 2007, Andi Kleen wrote: > > > > > OTOH, the accounting hook would allow us to remove the IRQ#0 -> > > > CPU#0 restriction. Not sure whether it's worth the trouble. > > > > Some SIS chipsets hang the machine when you migrate irq 0 to another > > CPU. It's better to keep that Also I wouldn't be surprised if there > > are some other assumptions about this elsewhere. > > > > Ok in theory it could be done only on SIS, but that probably would > > really not be worth the trouble > > Agreed. > > I just got a x8664-hrt report, where I found the following oddity: > > 0: 1197 172881 IO-APIC-edge timer > > That's one of those infamous AMD C1E boxen. Strange, all my systems > have IRQ#0 on CPU#0 and nowhere else. Any idea ? 2 things; the current irq balancers don't balance the timer interrupt, in fact they'll leave it alone (so the chipset might balance) older ones pin it to cpu 0 or rotate it.... - To unsubscribe from this list: send the line "unsubscribe linux-rt-users" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
