Hi all, Has anybody had any success in enabling the rk3399_dmc devfreq driver. I've been hacking on it for a few days now with very limited success. Our board has single channel lpddr4 which can run stable at either 400/800 MHz when set from the u-boot rk3399 sdram driver. I've tried numerous combinations such as: 1) mainline u-boot v2020.07-rc4 TPL (RAM init)/SPL+proper + mainline ATF + linux mainline 5.5.8 This locks up when attempting to set the ddr clock rate at this point: /* PHY_LOW_FREQ_SEL */ /* DENALI_PHY_913 1bit offset_0 */ if (timing_config->freq > 400) mmio_clrbits_32(PHY_REG(i, 913), 1); else mmio_setbits_32(PHY_REG(i, 913), 1); https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/rockchip/rk3399/drivers/dram/dfs.c#L1521 2) rockchip DDR init + mainline uboot SPL+proper + mainline ATF + linux mainline 5.5.8 This locks up at the same point as above. 3) rockchip DDR init + mainline uboot SPL+proper + rockchip binary ATF + linux mainline 5.5.8 This manages to set the rate but then instantly crashes the system, probably something to do with ram config options in the reconfiguration stage, but I have no view to this as the ATF is proprietary. If anybody has any documentation on this, or could point me in the direction of someone who does have documentation that would help a lot. Any war stories for others who have this working would also be appreciated, there have been some changes to this code fairly recently, so even though there are no current users in kernel, I assume someone somewhere has this working? Regards, Jack. _______________________________________________ Linux-rockchip mailing list Linux-rockchip@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/linux-rockchip
