Add PCIE_PHY clock enablement support on rk3399
clock driver.
This clock is enabled by default, so do nothing
if it triggers during the PCIe PHY probe other
PHY users on this clock will simply fail.
Signed-off-by: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx>
---
drivers/clk/rockchip/clk_rk3399.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index d822acace1..8e069fbade 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1071,12 +1071,27 @@ static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
return -ENOENT;
}
+static int rk3399_clk_enable(struct clk *clk)
+{
+ switch (clk->id) {
+ case SCLK_PCIEPHY_REF:
+ /* do nothing, clk is enabled by default */
+ break;
+ default:
+ debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
static struct clk_ops rk3399_clk_ops = {
.get_rate = rk3399_clk_get_rate,
.set_rate = rk3399_clk_set_rate,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.set_parent = rk3399_clk_set_parent,
#endif
+ .enable = rk3399_clk_enable,
};
#ifdef CONFIG_SPL_BUILD
--
2.17.1
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