在 2019/11/26 4:52, Peter Geis 写道:
Good Afternoon, I asked this question in my pcie bug report, but I think it got lost in the mess so I will ask it standalone. I noticed that there is a lot of code overlap between the shared dwc pcie driver and the rockchip driver. Is there a particular reason we aren't using the shared driver instead of reinventing the wheel?
That's because qcon and tegra do based on dwc IP and just add some vendor-specific registers but it's totally different case for rockchip, as you have noticed that the registers don't line up with dwc, that's said, they are totoally 2 IPs with different register layout. It's NOT the rule for how linux driver work.
I know that our registers don't seem to line up with the default dwc registers, but tegra and qcom both seem to implement custom registers. I started trying to write a dwc layer driver for the rockchip, but as I have very little experience with pcie I was quickly overwhelmed. Is there anything outright blocking the move to the shared driver?
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