Rename tsel_wr_select_p to tsel_wr_select_dq_p based
on the bsp code and associated datasheet.
No functionality change.
Signed-off-by: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx>
Signed-off-by: YouMin Chen <cym@xxxxxxxxxxxxxx>
---
drivers/ram/rockchip/sdram_rk3399.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 7c05814f19..780b18fa17 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -160,14 +160,14 @@ static void set_ds_odt(const struct chan_info *chan,
u32 *denali_phy = chan->publ->denali_phy;
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
- u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
+ u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
u32 reg_value;
if (sdram_params->base.dramtype == LPDDR4) {
tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
- tsel_wr_select_p = PHY_DRV_ODT_40;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_40;
ca_tsel_wr_select_p = PHY_DRV_ODT_40;
tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
@@ -177,7 +177,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_idle_select_n = PHY_DRV_ODT_240;
} else if (sdram_params->base.dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
- tsel_wr_select_p = PHY_DRV_ODT_34_3;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_p = PHY_DRV_ODT_48;
tsel_idle_select_p = PHY_DRV_ODT_240;
@@ -187,7 +187,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
- tsel_wr_select_p = PHY_DRV_ODT_34_3;
+ tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
tsel_idle_select_p = PHY_DRV_ODT_240;
@@ -211,7 +211,7 @@ static void set_ds_odt(const struct chan_info *chan,
* for write cycles for DQ/DM
*/
reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
- (tsel_wr_select_dq_n << 8) | (tsel_wr_select_p << 12) |
+ (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
(tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
@@ -251,7 +251,7 @@ static void set_ds_odt(const struct chan_info *chan,
/* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
clrsetbits_le32(&denali_phy[924], 0xff,
- tsel_wr_select_dq_n | (tsel_wr_select_p << 4));
+ tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
clrsetbits_le32(&denali_phy[925], 0xff,
tsel_rd_select_n | (tsel_rd_select_p << 4));
--
2.18.0.321.gffc6fa0e3
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