Am Freitag, 3. Mai 2019, 23:22:08 CEST schrieb Douglas Anderson:
> At boot time, my rk3288-veyron devices yell with 8 lines that look
> like this:
> [ 0.000000] rockchip_mmc_get_phase: invalid clk rate
>
> This is because the clock framework at clk_register() time tries to
> get the phase but we don't have a parent yet.
>
> While the errors appear to be harmless they are still ugly and, in
> general, we don't want yells like this in the log unless they are
> important.
>
> There's no real reason to be yelling here. We can still return
> -EINVAL to indicate that the phase makes no sense without a parent.
> If someone really tries to do tuning and the clock is reported as 0
> then we'll see the yells in rockchip_mmc_set_phase().
>
> Fixes: 4bf59902b500 ("clk: rockchip: Prevent calculating mmc phase if clock rate is zero")
> Signed-off-by: Douglas Anderson <dianders@xxxxxxxxxxxx>
applied for 5.3
Thanks
Heiko
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