Hi Mike, Stephen,
looks I can re-use my introduction from 4.20 and 5.0 - no big changes
again this time.
A rate_parent flag and some fixup for the fractional part of a PLL
So please pull.
Thanks
Heiko
The following changes since commit bfeffd155283772bbe78c6a05dec7c0128ee500c:
Linux 5.0-rc1 (2019-01-06 17:08:20 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/v5.1-rockchip-clk1
for you to fetch changes up to 491b00ff699356a8dab10eb517a1b44205514c9e:
clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks (2019-01-07 09:17:15 +0100)
----------------------------------------------------------------
Fix for PLL rate calculation on rk3328 and SET_RATE_PARENT flag
for the display clock on rk3066.
----------------------------------------------------------------
Finley Xiao (1):
clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks
Katsuhiro Suzuki (1):
clk: rockchip: fix frac settings of GPLL clock for rk3328
drivers/clk/rockchip/clk-rk3188.c | 4 ++--
drivers/clk/rockchip/clk-rk3328.c | 12 ++++++------
2 files changed, 8 insertions(+), 8 deletions(-)
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