On the firefly the vsel pins of the syr82x regulators are connected to
soc gpios, making them software controllable.
Right now the pins do not get configured at all, so cpu_b_sleep_h is
configured as input with a pull up while the gpu_sleep_h has a pull-down.
In contrast the pin names indicate both should be high in their sleep
state and low in normal operation and the fcs,suspend-voltage-selector
does mirror this setting, so enable the already existing pinctrl
entries for them and also fix their naming to match the schematics.
Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx>
---
arch/arm64/boot/dts/rockchip/rk3399-firefly.dts | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
index aaa485dbe081..ea63477ca9fe 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
@@ -456,6 +456,8 @@
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpu_b_sleep_h>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@@ -473,6 +475,8 @@
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpu_sleep_h>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@@ -589,11 +593,11 @@
};
pmic {
- vsel1_gpio: vsel1-gpio {
+ cpu_b_sleep_h: cpu-b-sleep-h {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
};
- vsel2_gpio: vsel2-gpio {
+ gpu_sleep_h: gpu-sleep-h {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
--
2.18.0
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