Hi, On Thu, Mar 15, 2018 at 8:02 PM, Lin Huang <hl at rock-chips.com> wrote: > These clocks do not assign default clock frequency, and use the > default cru register value to get frequency, so if cpll increase > frequency, these clocks also increase their frequency, that may > exceed their signed off frequency. So assign default clock for > them to avoid it. > > Change-Id: If79368aeda5c51dbf2a3b6659f17052a2ae4a401 > Signed-off-by: Lin Huang <hl at rock-chips.com> > --- > arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 8 +++++++- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 14 ++++++++++++-- > 2 files changed, 19 insertions(+), 3 deletions(-) This seems fine to me. For the previous similar change I liked the idea of explaining in the commit message why it's a good idea to include these rates in the CRU node even though the same CRU node explicitly sets the CPLL to 800 MHz. AKA, you could add to the commit message: NOTE: on none of the boards currently in mainline do we expect CPLL to be anything other than 800 MHz, but some future boards might have it. It's still good to be explicit about the clock rates to make diffing against future boards easier and also to rely less on BIOS muxing. > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > index 4550c0f..b358533 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -315,6 +315,8 @@ > clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, > <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; > clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; > + assigned-clocks = <&cru HCLK_SD>; > + assigned-clock-rates = <200000000>; To make things symmetric I'd probably also add a similar setting for hclk_sdio unless there's a reason that 200 MHz isn't the right rate there. Oh, actually, the clock tree isn't very symmetric here anyway, is it? For SDIO the clocks all come straight from "hclk_perilp1". I guess you could explicitly set "hclk_sdio", and "hclk_sdio_noc" (and "hclk_sdioaudio_noc"?) to 200 MHz. In any case, since it's not symmetric then I won't push for it being in this patch. Certainly the change in CPLL won't affect them since they're parented off hclk_peripl1 and we already have that taken care of... Reviewed-by: Douglas Anderson <dianders at chromium.org><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Mar 15, 2018 at 8:02 PM, Lin Huang <span dir="ltr"><<a href="mailto:hl at rock-chips.com" target="_blank">hl at rock-chips.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">These clocks do not assign default clock frequency, and use the<br> default cru register value to get frequency, so if cpll increase<br> frequency, these clocks also increase their frequency, that may<br> exceed their signed off frequency. So assign default clock for<br> them to avoid it.<br> <br> Change-Id: If79368aeda5c51dbf2a3b6659f170<wbr>52a2ae4a401<br> Signed-off-by: Lin Huang <<a href="mailto:hl at rock-chips.com">hl at rock-chips.com</a>><br> ---<br> arch/arm64/boot/dts/rockchip/<wbr>rk3399-gru.dtsi | 8 +++++++-<br> arch/arm64/boot/dts/rockchip/<wbr>rk3399.dtsi | 14 ++++++++++++--<br> 2 files changed, 19 insertions(+), 3 deletions(-)<br> <br> diff --git a/arch/arm64/boot/dts/<wbr>rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/<wbr>rockchip/rk3399-gru.dtsi<br> index 18f546f..84e367b 100644<br> --- a/arch/arm64/boot/dts/<wbr>rockchip/rk3399-gru.dtsi<br> +++ b/arch/arm64/boot/dts/<wbr>rockchip/rk3399-gru.dtsi<br> @@ -588,7 +588,10 @@<br> <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,<br> <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,<br> <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,<br> - <&cru ACLK_VIO>;<br> + <&cru ACLK_VIO>,<br> + <&cru ACLK_GIC_PRE>,<br> + <&cru PCLK_DDR>,<br> + <&cru ACLK_HDCP>;<br> assigned-clock-rates =<br> <600000000>, <800000000>,<br> <1000000000>,<br> @@ -597,6 +600,9 @@<br> <100000000>, <100000000>,<br> <50000000>, <800000000>,<br> <100000000>, <50000000>,<br> + <400000000>,<br> + <200000000>,<br> + <200000000>,<br> <400000000>;<br> };<br> <br> diff --git a/arch/arm64/boot/dts/<wbr>rockchip/rk3399.dtsi b/arch/arm64/boot/dts/<wbr>rockchip/rk3399.dtsi<br> index 4550c0f..b358533 100644<br> --- a/arch/arm64/boot/dts/<wbr>rockchip/rk3399.dtsi<br> +++ b/arch/arm64/boot/dts/<wbr>rockchip/rk3399.dtsi<br> @@ -315,6 +315,8 @@<br> clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,<br> <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;<br> clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";<br> + assigned-clocks = <&cru HCLK_SD>;<br> + assigned-clock-rates = <200000000>;<br> fifo-depth = <0x100>;<br> power-domains = <&power RK3399_PD_SD>;<br> resets = <&cru SRST_SDMMC>;<br> @@ -466,8 +468,10 @@<br> clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,<br> <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;<br> clock-names = "core-clk", "pclk", "spdif", "grf";<br> - phys = <&tcphy0_dp>, <&tcphy1_dp>;<br> + assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;<br> + assigned-clock-rates = <100000000>, <200000000>;<br> power-domains = <&power RK3399_PD_HDCP>;<br> + phys = <&tcphy0_dp>, <&tcphy1_dp>;<br> resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,<br> <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;<br> reset-names = "spdif", "dptx", "apb", "core";<br> @@ -1323,7 +1327,10 @@<br> <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,<br> <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,<br> <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,<br> - <&cru ACLK_VIO>;<br> + <&cru ACLK_VIO>,<br> + <&cru ACLK_GIC_PRE>,<br> + <&cru PCLK_DDR>,<br> + <&cru ACLK_HDCP>;<br> assigned-clock-rates =<br> <594000000>, <800000000>,<br> <1000000000>,<br> @@ -1332,6 +1339,9 @@<br> <100000000>, <100000000>,<br> <50000000>, <600000000>,<br> <100000000>, <50000000>,<br> + <400000000>,<br> + <200000000>,<br> + <200000000>,<br> <400000000>;<br> };<br> <span class="HOEnZb"><font color="#888888"><br> --<br> 2.7.4<br> <br> <br> ______________________________<wbr>_________________<br> Linux-rockchip mailing list<br> <a href="mailto:Linux-rockchip at lists.infradead.org">Linux-rockchip at lists.<wbr>infradead.org</a><br> <a href="http://lists.infradead.org/mailman/listinfo/linux-rockchip"; data-saferedirecturl="https://www.google.com/url?hl=en&q=http://lists.infradead.org/mailman/listinfo/linux-rockchip&source=gmail&ust=1521301078018000&usg=AFQjCNGCFi3WNAm5H3Wpohoas1jdNEBfOA"; rel="noreferrer" target="_blank">http://lists.infradead.org/<wbr>mailman/listinfo/linux-<wbr>rockchip</a><br> </font></span></blockquote></div><br></div>
