Hi, On Sun, Mar 11, 2018 at 6:50 PM, Shunqian Zheng <zhengsq at rock-chips.com> wrote: > The ACLK_VIO is a parent clock used by a several children, > its suggested clock rate is 400MHz. Right now it gets 400MHz > because it sources from CPLL(800M) and divides by 2 after reset. > It's good not to rely on default values like this, so let's > explicitly set it. > NOTE: it's expected that at least one board may override cru node and > set the CPLL to 1.6 GHz. On that board it will be very important to be > explicit about aclk-vio being 400 MHz. > > Signed-off-by: Shunqian Zheng <zhengsq at rock-chips.com> > --- > arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 6 ++++-- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++++-- > 2 files changed, 8 insertions(+), 4 deletions(-) Reviewed-by: Douglas Anderson <dianders at chromium.org>
