Am Montag, 5. M?rz 2018, 04:25:58 CET schrieb Shawn Lin: > The MMC sample and drv clock for rockchip platforms are derived from > the bus clock output to the MMC/SDIO card. So it should never happens > that the clk rate is zero given it should inherits the clock rate from > its parent. If something goes wrong and makes the clock rate to be zero, > the calculation would be wrong but may still make the mmc tuning process > work luckily. However it makes people harder to debug when the following > data transfer is unstable. > > Signed-off-by: Shawn Lin <shawn.lin at rock-chips.com> applied for 4.17 Thanks Heiko
