Hi Heiko, ? 2017/5/19 19:53, Heiko Stuebner ??: > Hi Shawn, > > Am Dienstag, 16. Mai 2017, 14:30:40 CEST schrieb Shawn Lin: >> In order to support multiple hierarchy of PCIe buses, >> for instance, PCIe switch, we need to extent bus-ranges >> to as max as possible. We have 32 regions and could support >> up to 31 buses except bus 0 for our root bridge. >> >> Signed-off-by: Shawn Lin <shawn.lin at rock-chips.com> > > can these 2 patches really be independent? yes, they are sloving two different issues, so I think they could be applied as-is. For patch 1, we was trying to ask PCI core to scan more buses as possible, otherwise it now only scan one, which isn't enough for PCIe switch chip. And before patch 2, we only allocated limited regions for devices attached to our root bridge, so we will fail to enable some devices if they ask more memory resource. > > I.e. what happens if only this patch1 is applied and patch2 is not? > [important for bisectability] > > > Heiko > >> --- >> >> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi >> index 25cb51d..532b89d 100644 >> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi >> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi >> @@ -220,7 +220,7 @@ >> #size-cells = <2>; >> #interrupt-cells = <1>; >> aspm-no-l0s; >> - bus-range = <0x0 0x1>; >> + bus-range = <0x0 0x1f>; >> clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, >> <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; >> clock-names = "aclk", "aclk-perf", >> > > > > >
