[PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399

[heiko@xxxxxxxxx (Heiko Stübner)]

Am Mittwoch, 18. Januar 2017, 12:20:56 CET schrieb Xing Zheng:
> The range of the  pclk_edp_div_con is [13:8] and 6 bits, not 5.
> 
> Reported-by: Lin Huang <hl at rock-chips.com>
> Signed-off-by: Xing Zheng <zhengxing at rock-chips.com>

applied for 4.11 with Lin's test tag


Thanks
Heiko