Hi Frank, Am Sonntag, 5. Februar 2017, 10:51:00 CET schrieb Frank Wang: > The original posting on Jan 19th have not received any responses, so I > resend them. > > The Current default dwc2 just handle one clock named otg, however, it may > have two or more clock need to manage for some new SoCs(such as RK3328), so > this adds change clk to clk's array of dwc2_hsotg to handle more clocks > operation. can you please give a bit more detail on the specific layout. I guess you're talking about hclk_otg_pmu, right? What component does it supply, because I didn't find anything in the partial TRM in the PMU section relating to the "otg". This meant to make sure, you're actually controlling some part of the dwc2 with that second/third/... clock and not some separate component. Heiko
