On 26/08/16 11:51, Shawn Lin wrote: > corecfg_clockmultiplier indicates clock multiplier value of > programmable clock generator which should be the same value > of SDHCI_CAPABILITIES_1. The default value of the register, > corecfg_clockmultiplier, is 0x10. But actually it is a mistake > by designer as our intention was to set it to be zero which > means we don't support programmable clock generator. So we have > to make it to be zero on bootloader which seems work fine until > now. But now we find an issue that when deploying genpd support > for it, the remove callback will trigger the genpd to poweroff the > power domain for sdhci-of-arasan which manage the controller, phy > and corecfg_* stuff. > > So when we do bind/unbind the driver, we have already reinit > the controller and phy, but without doing that for corecfg_*. > Regarding to only the corecfg_clockmultipler is wrong, let's > fix it by explicitly marking it to be zero when probing. With > this change, we could do bind/unbind successfully. > > Reported-by: Ziyuan Xu <xzy.xu at rock-chips.com> > Cc: Douglas Anderson <dianders at chromium.org> > Signed-off-by: Shawn Lin <shawn.lin at rock-chips.com> Acked-by: Adrian Hunter <adrian.hunter at intel.com>
