On Thu, Oct 06, 2016 at 04:50:00PM +0800, Shawn Lin wrote: > From: Brian Norris <briannorris at chromium.org> > > rk3399 supports PCIe 2.x link speeds marginally at best, and on some > boards, the link won't train at 5 GT/s at all. Rather than sacrifice 500 > ms waiting for training that will never happen, let's add a property > from devicetree to specify link capability. > > Signed-off-by: Brian Norris <briannorris at chromium.org> > Signed-off-by: Shawn Lin <shawn.lin at rock-chips.com> > > --- > > Changes in v4: > - define link_gen as u32 > - elaborate more for rockchip,max-link-speed on doc > > Changes in v3: > - Cast a warning for invalid max link speed and use gen1 for it. > That looks better than v2. (Suggested by Brian) > > Changes in v2: > - rename the property to rockchip,max-link-speed according to > Bjorn's recommendation and take some bits from imx6q-pcie to > make this requirement more consisent. > > .../devicetree/bindings/pci/rockchip-pcie.txt | 4 ++ > drivers/pci/host/pcie-rockchip.c | 63 ++++++++++++++-------- > 2 files changed, 44 insertions(+), 23 deletions(-) Not sure if it means anything much, since I wrote half of this, but: Reviewed-by: Brian Norris <briannorris at chromium.org>
