Am Mittwoch, 2. November 2016, 16:43:24 CET schrieb Julius Werner: > Rockchip RK3399 PLLs can be used in two separate modes: integral and > fractional. We can select between these two modes with the unambiguously > named DSMPD bit. > > During boot, we check all PLL settings to confirm that they match our > PLL table for that frequency, and reinitialize the PLLs where they > don't. The settings checked for this include the fractional divider > field that is only used in fractional mode, even if we're in integral > mode (DSMPD = 1) and that field has no effect. > > This patch changes the check to only compare the fractional divider if > we're actually in fractional mode. This way, we won't reinitialize the > PLL in cases where there's absolutely no reason for that, which may > avoid glitching child clocks that should better not be glitched (e.g. > PWM regulators). > > Signed-off-by: Julius Werner <jwerner at chromium.org> I took the liberty to clone the fix to the rk3036 pll type as well, which is quite similar and only differs in the actual register layout. As sugested by the above, I've applied this to my clk branch for 4.10 [0] Thanks for fixing this Heiko [0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?id=bf92384b6d729b22916ba832b4a225ca196e98ba
