On Wed, May 25, 2016 at 1:51 AM, Xing Zheng <zhengxing at rock-chips.com> wrote:
> Like rk3288, the pclk supplying the watchdog is controlled via the
> SGRF register area. Additionally the SGRF isn't even writable in
> every boot mode.
>
> But still the clock control is available and in the future someone
> might want to use it. Therefore define a simple clock for the time
> being so that the watchdog driver can read its rate.
>
> Signed-off-by: Xing Zheng <zhengxing at rock-chips.com>
> ---
>
> drivers/clk/rockchip/clk-rk3399.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
> index 291543f..b6742fa 100644
> --- a/drivers/clk/rockchip/clk-rk3399.c
> +++ b/drivers/clk/rockchip/clk-rk3399.c
> @@ -1498,6 +1498,7 @@ static void __init rk3399_clk_init(struct device_node *np)
> {
> struct rockchip_clk_provider *ctx;
> void __iomem *reg_base;
> + struct clk *clk;
>
> reg_base = of_iomap(np, 0);
> if (!reg_base) {
> @@ -1511,6 +1512,14 @@ static void __init rk3399_clk_init(struct device_node *np)
> return;
> }
>
> + /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
> + clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1);
> + if (IS_ERR(clk))
> + pr_warn("%s: could not register clock pclk_wdt: %ld\n",
> + __func__, PTR_ERR(clk));
> + else
> + rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
> +
> rockchip_clk_register_plls(ctx, rk3399_pll_clks,
> ARRAY_SIZE(rk3399_pll_clks), -1);
>
> --
> 1.7.9.5
>
>
Reviewed-by: Stephen Barber <smbarber at chromium.org>
Steve
