On 06/12/2016 07:10 PM, Frank Wang wrote:
> The newer SoCs (rk3366, rk3399) take a different usb-phy IP block
> than rk3288 and before, and most of phy-related registers are also
> different from the past, so a new phy driver is required necessarily.
>
> Signed-off-by: Frank Wang <frank.wang at rock-chips.com>
> ---
>
[ ... ]
> +
> +static int rockchip_usb2phy_resume(struct phy *phy)
> +{
> + struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
> + struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
> + int ret;
> +
> + dev_dbg(&rport->phy->dev, "port resume\n");
> +
> + ret = clk_prepare_enable(rphy->clk480m);
> + if (ret)
> + return ret;
> +
> + ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
> + if (ret)
> + return ret;
> +
> + rport->suspended = false;
> + return 0;
> +}
> +
> +static int rockchip_usb2phy_suspend(struct phy *phy)
> +{
> + struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
> + struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
> + int ret;
> +
> + dev_dbg(&rport->phy->dev, "port suspend\n");
> +
> + ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
> + if (ret)
> + return ret;
> +
> + rport->suspended = true;
> + clk_disable_unprepare(rphy->clk480m);
> + return 0;
> +}
> +
I am still quite confused by the clock handling.
The above will be called for each instantiated phy (user, otg).
Each time, clk_disable_unprepare() will be called. Yet, there
is no matching clk_prepare_enable() call during initialization.
How does this work ?
Thanks,
Guenter
