>From code inspection, it appears to be unsafe to do a read-modify-write of PCGCTL in dwc2_port_resume(). Let's make sure the spinlock is held around this operation. Signed-off-by: Douglas Anderson <dianders at chromium.org> --- drivers/usb/dwc2/hcd.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index af4e4a2..e79baf7 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -1500,6 +1500,8 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg) u32 hprt0; u32 pcgctl; + spin_lock_irqsave(&hsotg->lock, flags); + /* * If hibernation is supported, Phy clock is already resumed * after registers restore. @@ -1508,10 +1510,11 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg) pcgctl = dwc2_readl(hsotg->regs + PCGCTL); pcgctl &= ~PCGCTL_STOPPCLK; dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + spin_unlock_irqrestore(&hsotg->lock, flags); usleep_range(20000, 40000); + spin_lock_irqsave(&hsotg->lock, flags); } - spin_lock_irqsave(&hsotg->lock, flags); hprt0 = dwc2_read_hprt0(hsotg); hprt0 |= HPRT0_RES; hprt0 &= ~HPRT0_SUSP; -- 2.6.0.rc2.230.g3dd15c0
